低复杂度Reed-Solomon解码器在地震勘探仪器中的应用
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摘要
针对地震勘探仪器,本文提出了一种RiBM(reformulated inversionless berlekamp-massy)算法的改进算法——ARiBM(area-efficient RiBM)算法。RiBM算法是一种阵列式的并行结构,其优点是解码速度快,所有处理单元的结构都相同,缺点是解码器占用的逻辑资源大。利用RiBM算法中处理单元结构相同的优势,ARiBM将RiBM算法中的运算量展开,大大提高了处理单元的利用率,降低了解码器占用的逻辑资源。大型地震采集系统具有逻辑资源要求苛刻、解码速度相对容易满足等特点,与ARiBM算法的特性完全吻合,因此,ARiBM算法有望在类似的系统中得到广泛应用。
Aiming at seismic exploration instrument,this paper proposes a modified RiBM(Reformulated inversionless Berlekamp-Massy) algorithm-ARiBM(Area-efficient RiBM).RiBM algorithm is a kind of systolic array architecture; its advantages are fast decoding speed and all processing elements(PEs) have a unified form.The disadvantage of RiBM is high complexity in logic resource.With the advantage of unified PEs,ARiBM expands the systolic array architecture of RiBM serially,so that the utilization of PEs is optimized and the logic resource is reduced greatly.Large-scale seismic acquisition system(LSAS) has strait logic resource constraint and relatively low decoding speed requirement,which match the characteristics of ARiBM algorithm well,so the ARiBM algorithm is expected to be applied in similar system widely.
Aiming at seismic exploration instrument,this paper proposes a modified RiBM(Reformulated inversionless Berlekamp-Massy) algorithm-ARiBM(Area-efficient RiBM).RiBM algorithm is a kind of systolic array architecture; its advantages are fast decoding speed and all processing elements(PEs) have a unified form.The disadvantage of RiBM is high complexity in logic resource.With the advantage of unified PEs,ARiBM expands the systolic array architecture of RiBM serially,so that the utilization of PEs is optimized and the logic resource is reduced greatly.Large-scale seismic acquisition system(LSAS) has strait logic resource constraint and relatively low decoding speed requirement,which match the characteristics of ARiBM algorithm well,so the ARiBM algorithm is expected to be applied in similar system widely.
引文
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[13]SHAO H M,TRUONG T K,Deutsch L J,et al.A VLSI design of a pipeline reed-solomon decoder[J].IEEE Transactions on Computers,1985,C-34(5):393-403.
[14]Rizwan Shahid.Retimed Decomposed Serial Berlekamp-Massey (BM ) Architecture for High-Speed Reed-Solomon Decoding[C].Proceedings of the IEEE International Frequency Control Symposium and Exposition,Hyderabad, India,2008:53-58.
[15]申飞,吴仲城,孟明,等.网络化传感器节点的低功耗设计[J].仪器仪表学报,2004,25(S1):259-260. SHENF,WU ZH CH,MENG M,et al.Low-power Design Technique for Networked Sensor Node[J].Chinese Journal of Scientific Instrument,2004,25(S1): 259-260.
[2]李军科,张俊,顾亚平.BCH分组码原理、实现及纠错性能分析[J].仪器仪表学报,2004,25(S1): 518-519. LI J K,ZHANG J,GU Y P.BCH Encoding Application and analysis of error-correcting property[J].Chinese Journal of Scientific Instrument,2004,25(S1): 518-519.
[3]殷致云,柯熙政,张波.无线激光通信中GF(3)域上的纠错编码研究[J].电子测量与仪器学报,2009,23 (7):23-28. YIN ZH Y,KE X ZH,ZHANG B.Research on errorcorrecting code in wireless laser communications over GF (3)[J].Journal of Electronic Measurement and Instrument 2009,23(7):23-28.
[4]LEE H H.High-speed VLSI architecture for parallel Reed-Solomon decoder[J].IEEE Transactions on Very Large Scale Integration(VLSI) Systems,2003,11(2):288-294.
[5]WANGC C,TRUONGTK,SHAO H M,etal.VLSI Architectures for Computing Multiplications and Inverses in GF(2m)[J].IEEE Transactions on Computers, 1985,C-34(8):709-717.
[6]DRESCHER W,FETTWEIS G.VLSI architectures for multiplication in GF(2m) for application tailored digital signal processors[C].IEEE Workshop on VLSI Signal Processing,San Francisco,CA,USA,1996:55-64.
[7]FURNESS R,BENAISSA M,FENN S T J,GF(2m) multiplication over triangular basis for design of Reed-Solomon codes[J].IEE Proceedings:Computers and Digital Techniques,1998,145(6):437-443.
[8]FENN S T J,BENAISSA M,TAYLOR D,GF(2m) multiplication and division over the dual basis[J]. IEEE Transactions on Computers,1996,45(3 ): 319-327.
[9]ARASH R M,ANWAR H M.Low complexity bit parallel architectures for polynomial basis multiplication over GF (2m)[J].IEEE Transactions on Computers,2004,53 (8 ):945-959.
[10]SARWATE D V,SHANBHAG N R,High-speed architectures for Reed-Solomon decoders[J].IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2001,9(5):641-655.
[11]KAVISH S,VISWAJITH K N,SRINIVASAN S,et al. Ultra folded high-speed architectures for Reed Solomon decoders[C].Proceedings of the IEEE International Conference on VLSI Design,Hyderabad,India,2006: 517-520.
[12]SHAOH M,REEDIS.On the VLSI design ofapipeline Reed-Solomon decoder using systolic arrays[J]. IEEE Transactions on Computers,1988,37(10):1273- 1280.
[13]SHAO H M,TRUONG T K,Deutsch L J,et al.A VLSI design of a pipeline reed-solomon decoder[J].IEEE Transactions on Computers,1985,C-34(5):393-403.
[14]Rizwan Shahid.Retimed Decomposed Serial Berlekamp-Massey (BM ) Architecture for High-Speed Reed-Solomon Decoding[C].Proceedings of the IEEE International Frequency Control Symposium and Exposition,Hyderabad, India,2008:53-58.
[15]申飞,吴仲城,孟明,等.网络化传感器节点的低功耗设计[J].仪器仪表学报,2004,25(S1):259-260. SHENF,WU ZH CH,MENG M,et al.Low-power Design Technique for Networked Sensor Node[J].Chinese Journal of Scientific Instrument,2004,25(S1): 259-260.
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