Baseband implementation of OTR-UWB receiver using FPGA

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• 作者：Hossein Gharaee ; Abdolreza Nabavi
• 关键词：UWB ; OTR-UWB ; Synchronization ; FPGA ; Synthesis
• 刊名：AEU - International Journal of Electronics and Communications
• 出版年：2010
• 出版时间：March 2010
• 年：2010
• 卷：64
• 期：3
• 页码：258-266
• 全文大小：419 K

文摘

This paper presents a new transmitted reference ultra-wideband receiver, which utilizes the orthogonal property of even and odd order derivatives of Gaussian pulses in neighboring chips for synchronization. This system, referred to as orthogonal TR-UWB (OTR-UWB), employs only a single spreading code, which results in much lower mean detection time compared to DS-UWB systems since smaller search space is involved for coarse acquisition. The hardware complexity for OTR-UWB receiver is significantly reduced against conventional TR-UWB systems. In addition, simulation results show that bit error rate (BER) performance is improved, while the new system is capable of supporting higher data rates. Also, this paper presents a technique for implementing low rate OTR-UWB system in FPGA by combining pipeline scheduling, parallel component, and module selection. The system has been implemented on two FPGA platforms from ALTERA and XILINX, CycloneII (EP2C35F672C6) and Spartan 3 (3s4000fg676-5)with a bit-rate of 25Mb/s without using equalizer. It incorporates 4-bit of resolution with 8GHz frequency sampling rate for analog to digital conversion realized by parallel low frequencyADC blocks. Gate estimation and power analysis are performed by Quartus II 7.1 (ALTERA) and ISE 8.1 (XILINX) softwares.