Low power SRAM design for 14 nm GAA Si-nanowire technology

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• 作者：Gaurav Kaushal^a ; H. Jeong^a ; Satish Maheshwaram^b ; S.K. Manhas^b ; ^{samanfec@iitr.ac.in" class="auth_mail" title="E-mail the corresponding author} ; S. Dasgupta^b ; S.O. Jung^a ; ^{sjung@yonsei.ac.kr" class="auth_mail" title="E-mail the corresponding author}
• 关键词：Gate-all-around ; Si-nanowire FET ; SRAM cell
• 刊名：Microelectronics Journal
• 出版年：2015
• 出版时间：December 2015
• 年：2015
• 卷：46
• 期：12
• 页码：1239-1247
• 全文大小：1954 K

文摘

This paper presents a low power and stable 6-T nanowire SRAM cell design by tuning the extension length of the access transistor. Our approach significantly reduces the power dissipation with a low active area and improves the SRAM cell read stability. We utilize device design parameters such as the nanowire diameter, the number of nanowires, and the device extension length to improve the stability of the SRAM cells. We find that the extension length tuning technique exhibits 15% and ~60% savings in active area and static power consumption, respectively, in comparison to a conventional multi-nanowire tuning technique. In addition, the proposed technique achieves 6% and 8% improvements in the read and hold noise margins, respectively, with a 6.5% decrease in write noise margin and a ~14% increase in the read/write access time. Our results show that the extension length-tuned access transistor is an excellent option for improving the satiability with low power for sub-14-nm technologies.