The research and design of reconfigurable computing for Block cipher
详细信息    查看全文
  • 作者:Xiaohui Yang (1)
    Zibin Dai (1)
    Yongfu Zhang (1)
    Xuerong Yu (1)
  • 关键词:Reconfigurable computing ; Block cipher ; Reconfigurable Cryptographic for Block ciphers Architecture (RCBA) ; TP309.7
  • 刊名:Journal of Electronics (China)
  • 出版年:2008
  • 出版时间:July 2008
  • 年:2008
  • 卷:25
  • 期:4
  • 页码:503-510
  • 全文大小:225KB
  • 参考文献:1. R. Atkinson. Security architecture for the internet protocol. IETF Draft Architecture ipsec-arch-sec00, 1996.
    2. P. Fergguson and G. Huston. What is a VPN. http://www.employees.org/ferguson/vpn.pdf, 1998.
    3. Adam J. Elbirt. Reconfigurable computing for symmetric-key algorithms. [Ph.D. dissertation], Electrical and Computer Engineering Department, University of Massachusetts Lowell, April 22, 2002.
    4. J. Dray. NIST performance analysis of the final round Java?AES candidates. In The Third Advanced Encryption Standard Candidate Conference, New York, USA, April 13-4, 2000, 149-60.
    5. K. Aoki and H. Lipmaa. Fast implementations of AES candidates. In The Third Advanced Encryption Standard Candidate Conference, New York, USA, April 13-4, 2000, 106-22.
    6. B. Schneier. Applied Cryptography. John Wiley & Sons Inc, New York, USA, 2nd ed., 1996, 78-1.
    7. R. Doud. Hardware crypto solutions boost VPN. / Electronic Engineering Times, 1056(1999)12, 57-4.
    8. A. J. Elbirt. Instruction-level distributed processing for sysmmetric-key cryptography. / IEEE Trans. on Parallel and Distributed Systems, 16(2005)5, 468-80. CrossRef
    9. M. Wazlowski, L. Agarwal, A. Smith, E. Lam, P. Athanas, H. Silverman, and S. Ghosh. PRISM-II: Compiler and architecture. In Workshop FPGAs and Custom Computing Machines (FCCM-3), Napa Valley, California, April 5-, 1993, 29-6.
    10. H. Singh, M. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho. MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications. / IEEE Trans. on Computers, 49(2000)5, 465-81. CrossRef
    11. R. Reed Taylor and Seth Copen Goldstein. A high-performance flexible architecture for cryptography. Proceedings of the 1st international Workshop on Cryptographic Hardware and Embedded Systems(CHES-9), Worcester, MA, USA, August 12-3, 1999, vol.1717, 231-45.
    12. M. J. Wirthlin and B. L. Hutchings. A dynamic instruction set computer. In Workshop FPGAs and Custom Computing Machines (FCCM-5), Napa Valley, California, April 19-1, 1995, 99-07.
    13. R. D. Witting and P. Chow. OneChip: An FPGA processor with reconfigurable logic. In Worshop FPGAs and Custom Computing Machines (FCCM-6), Napa Valley, California, April 17-9, 1996, 126-35.
    14. J. R. Hauser and J. Wawrzynek. Garp: A MIPS processor with a reconfigurable coprocessor. In Workshop FPGAs and Custom Computing Machines (FCCM-7), Napa Valley, California, April 16-8, 1997, 12-1.
    15. S. Hauck, T. Fry, M. Hosler, and J. Kao. The chimaera reconfigurable functional unit. In Workshop FPGAs and Custom Computing Machines (FCCM-7), Napa Valley, California, April 16-8, 1997, 87-6.
    16. C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, and H. Holt. The NAPA adaptive processing architecture. In Workshop FPGAs and Custom Computing Machines (FCCM-8), Napa Valley, California, April 15-7, 1998, 28-7.
    17. T. Miyamori, and U. Olukotun. A quantitative analysis of reconfigurable coprocessors for multimedia applications. FPGAs for Custom Computing Machines (FCCM-8), Napa Valley, California, April 15-7, 1998, 2-1.
    18. J. A. Jacob and P. Cow. Memory interfacing and instruction specification for reconfigurable processors. Seventh International Symposium on Field-Programmable Gate Array (FPGA-9), Monterey, California, USA, February 21-3, 1999, 145-54.
    19. G. Sassatelli, G. Cambon, J. Galy, and L. Torres. A dynamically reconfigurable architecture for embedded systems. Proceedings of the 12th International Workshop on Rapid System Prototyping (RSP) 2001, Monterey, California, USA, June 25-7, 2001, 32-7.
    20. H. Singh, M. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho. MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications. / IEEE Trans. on Computers, 49(2000)5, 465-81. CrossRef
    21. Altera Corporation. Stratix II architecture. Available at http://www.Altera.com, February 2004.
    22. Crypto++5.1 Bechmarks[EB]. http://www.eskimo.com/~weidai/benchmarks.html, August 2005.
  • 作者单位:Xiaohui Yang (1)
    Zibin Dai (1)
    Yongfu Zhang (1)
    Xuerong Yu (1)

    1. Institute of Electronic Technology, The PLA Information Engineering University, Zhengzhou, 450004, China
  • ISSN:1993-0615
文摘
This paper describes a new specialized Reconfigurable Cryptographic for Block ciphers Architecture (RCBA). Application-specific computation pipelines can be configured according to the characteristics of the block cipher processing in RCBA, which delivers high performance for cryptographic applications. RCBA adopts a coarse-grained reconfigurable architecture that mixes the appropriate amount of static configurations with dynamic configurations. RCBA has been implemented based on Altera’s FPGA, and representative algorithms of block cipher such as DES, Rijndael and RC6 have been mapped on RCBA architecture successfully. System performance has been analyzed, and from the analysis it is demonstrated that the RCBA architecture can achieve more flexibility and efficiency when compared with other implementations.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700