无片上电感的低功耗高线性度CMOS混频器
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摘要
物联网设备的数量将在不久的将来得到快速增长。延长电池寿命、提高信号动态范围是物联网通信系统射频前端的主要关注点。为解决射频前端功耗和线性度的问题,提出了一种改进型的吉尔伯特混频器。相比于传统吉尔伯特混频器,该混频器在跨导级采用工作在亚阈值区的PMOS/NMOS互补结构,结合了电流复用技术和导数叠加技术,实现了功耗和线性度的折中;并采用交叉电容耦合形成负阻抗,抵消了寄生电容的影响,从而在低功耗情况下提高了线性度。基于HHNEC 0.18μm Bi CMOS工艺后仿真结果表明,该混频器在射频频率0.4～3 GHz时转换增益为6.2～7.6 d B,在2.4 GHz频率下输入三阶交调点(input third-order intercept point,IIP3)为14.96 d Bm,在电源电压为1 V的情况下功耗为1.8 m W。该混频器核心电路尺寸为460μm×190μm。与相关工作对比,该混频器具有低功耗、高线性度的特点。
The number of internet of things( IOT) devices is expected to increase rapidly in the near future. Prolonging battery life and improving signal dynamic range of RF front end of the communication system are the major concerns for IOT applications. In order to solve the problem of RF power consumption and linearity,a novel Gilbert mixer is proposed. Compared with the conventional Gilbert mixer,the proposed mixer utilizes subthreshold PMOS/NMOS complementary structure at the transconductance stage and combines the current reuse and derivative superposition technologies,realizing a trade-off between power consumption and linearity. The mixer also employs two cross-coupling capacitors to generate the negative impedance which cancels parasitic capacitance,achieving high linearity with low power consumption. Implemented in HHNEC0.18 μm Bi CMOS process,the post simulation results show that the mixer has a gain of 6.2 ～ 7.6 d B from 0.4 GHz to 3 GHz and a IIP3 of 14.96 d Bm at 2.4 GHz while having a power consumption of 1.8 m W from 1 V supply voltage. The mixer core circuit size is 460 μm × 190 μm. Compared with other work,the mixer has the advantages of low power consumption and high linearity.
The number of internet of things( IOT) devices is expected to increase rapidly in the near future. Prolonging battery life and improving signal dynamic range of RF front end of the communication system are the major concerns for IOT applications. In order to solve the problem of RF power consumption and linearity,a novel Gilbert mixer is proposed. Compared with the conventional Gilbert mixer,the proposed mixer utilizes subthreshold PMOS/NMOS complementary structure at the transconductance stage and combines the current reuse and derivative superposition technologies,realizing a trade-off between power consumption and linearity. The mixer also employs two cross-coupling capacitors to generate the negative impedance which cancels parasitic capacitance,achieving high linearity with low power consumption. Implemented in HHNEC0.18 μm Bi CMOS process,the post simulation results show that the mixer has a gain of 6.2 ～ 7.6 d B from 0.4 GHz to 3 GHz and a IIP3 of 14.96 d Bm at 2.4 GHz while having a power consumption of 1.8 m W from 1 V supply voltage. The mixer core circuit size is 460 μm × 190 μm. Compared with other work,the mixer has the advantages of low power consumption and high linearity.
引文
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[10] CORDOVA D,BAMPI S,FABRIS E. A CMOS downconversion mixer with high IIP2 and IIP3 for multi-band and multiple standards[C]//Symposium on Integrated Circuits and Systems Design(SBCCI). Aracaju,Brazil:IEEE,2014:1-7.
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[12] SOLATI P,YAVARI M,SOLATI P,et al. A wide-band CMOS active mixer with linearity improvement technique[C]//Iranian Conference on Electrical Engineering. Tehran,Iran:IEEE,2017:271-275.
[13]岳宏卫,王豪,韦保林.一种0.5~5 GHz改进型折叠混频器[J].微电子学,2017,47(3):372-374.YUE Hongwei,WANG Hao,WEI Baolin. An improved0.5~5 GHz folded mixer[J]. Microelectronics,2017,47(3):372-374.
[2] XU L,WANG K,CHANG C H,et al.Inductorless linearization of low-power active mixers[C]//IEEE International Symposium on Circuits and Systems. Lisbon,Portugal:IEEE,2015:2213-2216.
[3]郭本青,文光俊.一种低闪烁噪声高线性度WLAN混频器的设计[J].微电子学,2012,42(2):210-214.GUO Benqing,WEN Guangjun. Design of a WLAN mixer with low flicker noise and high linearity[J]. Microelectronics,2012,42(2):210-214.
[4] CHENG W,ANNEMA A J,WIENK G J M,et al.Aflicker noise/IM3 cancellation technique for active mixer using negative impedance[J]. IEEE Journal of SolidState Circuits,2013,48(10):2390-2402.
[5]张雷鸣,张金灿,刘博.一种改进的高线性CMOS混频器的分析与设计[J].微电子学,2016,46(2):219-223.ZHANGLeiming,ZHANG Jincan,LIU Bo. Analysis and design of an improved high linearity CMOS mixer[J]. Microelectronics,2016,46(2):219-223.
[6] MOLLAALIPOUR M,MIAR-NAIMI H. Animproved high linearity active CMOS mixer:design and Volterra series analysis[J]. IEEE Transactions on Circuits&Systems I Regular Papers,2013,60(8):2092-2103.
[7]申晶,张晓林.基于衬底偏置的超低耗电流复用混频器[J].北京航空航天大学学报,2013,39(4):531-534.SHEN Jing,ZHANGXiaolin. Ultra-low power bulk-biased mixer with current-use[J]. Journal of Beijing University of Aeronautics and Astronautics,2013,39(4):531-534.
[8] APARIN V. Linearizationof CDMA receiver front-ends[J]. Dissertation Abstracts International,2005,66-03(B):1614.
[9] PARVIZI M,NABAVI A. Highly linear common-gate mixer employing intrinsic second and third order distortion cancellation[J]. Ieice Electron Express,2009,6(6):310-316.
[10] CORDOVA D,BAMPI S,FABRIS E. A CMOS downconversion mixer with high IIP2 and IIP3 for multi-band and multiple standards[C]//Symposium on Integrated Circuits and Systems Design(SBCCI). Aracaju,Brazil:IEEE,2014:1-7.
[11] BHATT D,MUKHERJEE J,REDOUTEJ M. Low-power linear bulk-injection mixer for wide-band applications[J].IEEE Microwave&Wireless Components Letters,2016,26(10):828-830.
[12] SOLATI P,YAVARI M,SOLATI P,et al. A wide-band CMOS active mixer with linearity improvement technique[C]//Iranian Conference on Electrical Engineering. Tehran,Iran:IEEE,2017:271-275.
[13]岳宏卫,王豪,韦保林.一种0.5~5 GHz改进型折叠混频器[J].微电子学,2017,47(3):372-374.YUE Hongwei,WANG Hao,WEI Baolin. An improved0.5~5 GHz folded mixer[J]. Microelectronics,2017,47(3):372-374.