基于并行Flash的USB3.0中扰码-解扰码器的设计与实现
详细信息    查看全文 | 推荐本文 |
  • 英文篇名:Design and Realization of Scrambler_descrambler In USB3.0 Based on Parallel Flash
  • 作者:尹旭东
  • 英文作者:YIN Xudong;Institute of Electronic Science and Applied Physics,Hefei University of Technology;
  • 关键词:USB3.0 ; 扰码-解扰码器 ; 线性反馈移位寄存器 ; 并行flash
  • 英文关键词:B3.0;;scrambler and descrambler;;linear feedback shift register;;parallel flash
  • 中文刊名:JSSG
  • 英文刊名:Computer & Digital Engineering
  • 机构:合肥工业大学电子科学与应用物理学院;
  • 出版日期:2018-02-20
  • 出版单位:计算机与数字工程
  • 年:2018
  • 期:v.46;No.340
  • 语种:中文;
  • 页:JSSG201802041
  • 页数:4
  • CN:02
  • ISSN:42-1372/TP
  • 分类号:208-211
摘要
USB3.0是一种由Intel和Microsoft公司发起创立的接口规范,它以USB2.0作为基础实现了接口技术的进一步发展。数据的加扰与解扰是通信系统中的重要环节[2],在USB3.0系统中的链路层与物理层也需要用到加解扰技术来实现数据的准时、正确传送与接收[3]。论文按照USB3.0协议的要求,在扰码与解扰码的原理基础上,提出一种基于并行flash来快速高效实现扰码与解扰码的技术。整个设计经仿真和综合后能够在FPGA开发板上实现,结果表明所设计出来的扰码-解码器不仅满足USB3.0数据通信协议要求,还具备快速、高效、低复杂度和高可靠性的特点,使其具有一定的工程实际应用价值。
        USB3.0 is a interface specification launched by Intel and Microsoft,it is based on USB2.0 and it further develops the technology. Scrambler and descrambler are important parts in communication system. The Scrambler and descrambler are used to ensure the data send and receive correctly in the link layer and physical layer of USB3.0. This paper proposes a fast and efficient implementation based on the parallel flash according to the USB3.0 protocol. The design can through simulation and synthesis. It is also can be implemented on FPGA board. The result show the Scrambler and descrambler not only meet the requirements of USB3.0 communication protocol,and also has the characteristics of fast,efficient,low complexity and high reliability. It has a certain value in engineering application.
引文
[1]沈泊,温涛,孙承绶.M序列伪随机码发生器的低功耗实现[J].微电子学,1999,29(1):2-3.SHEN Po,WEN Tao,SUN Chengshou.The low power con-sumption of M sequence pseudo random code generator[J].Journal of Microelectronics,1999,29(1):2-3.
    [2]李永忠.现代通信原理与技术[M].北京:国防工业出版社,2010:273-279.LI Yongzhong.Modern Communication Principle andTechnology[M].Beijing:National Defence Industry Press,2010:273-279.
    [3]赵光.USB3.0物理层发送端的研究与设计[D].成都:电子科技大学,2009.ZHAO Guang.The Research and Design of The Sendingon The USB3.0 Physical Layer[D].Chengdu:Universityof Electronic Science and Technology,2009.
    [4]LEE S H,LEE P J.高速传输系统集成并行扰码器设计[C]//电气工程师学会,1988:361-364.LEE S H,LEE P J.Integrated parallel scrambler designfor high-speed transmission systems[C]//IEE,1988:361-364.
    [5]USB3.0规范[S].英特尔公司,2008:60-61.Universal Serial Bus3.0 Specification[S].Intel Corporation,2008:60-61.
    [6]张羿猛,黄芝平,毕占坤,等.并行帧同步扰码器的扩充比特设计法[J].光子学报,2006,35(7):1048-1051.ZHANG Yimeng,HUANG Zhiping,BI Zhankun,et al.The Method of Bit Expansion Design on Parallel FrameSynchronization Scrambler[J].Journal of Photons,2006,35(7):1048-1051.
    [7]段俊红,韩冰,王松,等.USB3.0数据传输协议分析及实现[J].信息安全与保密,2013,12(3):124-126.DUAN Junhong,HAN Bing,WANG Song,et al.The DataTransmission Protocol Analysis and Realization of USB3.0[J].Information Security and Secrecy,2013,12(3):124-126.
    [8]陈顺林,杨万全,董庆蓉.M序列在移动通信扰码中的应用及仿真[J].现代电子技术,2002(3):27-28.CHEN Shunlin,YANG Wanquan,DONG Qingrong.TheApplicationg and Simulation of M Sequence in The MobileCommunication Scrambler[J].The Modern ElectronicTechnology,2002(3):27-28.
    [9]付少忠,杨家韦.并行扰码和解扰的实现[J].无线电工程,2004,34(2):61-63.FU Shaozhong,YANG Jiawei.The Implementation of Par-allel Scrambler and Descrambler[J].The Radio Engineer-ing,2004,34(2):61-63.
    [10]易茂祥,章浩,郭红卫,等.m-序列扰码技术及其在SATA中的应用[J].微电子学,2012,42(4):502-505.YI Maoxiang,ZHANG Hao,GUO Hongwei,et al.M-se-quence Scrambler Technology and Its Application in SA-TA[J].Journal of Microelectronics,2012,42(4):502-505.
    [11]林浒,张荣茂.FPGA的设计与开发[J].小型微型计算机系统,1992,13(12):10-15.LIN Hu,ZHANG Rongmao.The Design and Develop-ment of FPGA[J].The Small Microcomputer System,1992,13(12):10-15.