一种高稳定性低功耗自偏置锁相环设计
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摘要
设计了一种高稳定性低功耗的自偏置锁相环,采用单电荷泵结构,并加入了快速启动电路,在不增加功耗的前提下,减小了环路的锁定时间。电路具有固定的阻尼因子,同时通过推导计算,确定了电路参数,使电路处于相位裕度最佳点附近,因此提高了锁相环(PLL)电路的稳定性。在SMIC 40 nm CMOS工艺模型下仿真,结果表明,该PLL电路工作频率范围为62.5～1500 MHz,在500 MHz输出频率的相位噪声为-97.56 d Bc@1 MHz,1.1 V电源供电下消耗功耗2.5 mW。输出频率为500 MHz时,锁定时间小于2μs。
A self-biased phase-locked-loop with high stability and low power consumption is designed. The circuit uses a single charge pump structure, and a quick start module is added at the same time. The locking time of the loop is reduced without increasing power consumption. The circuit has a fixed damping factor and the circuit parameters are determined through derivation and calculation to keep the circuit lying near the optimal point of phase margin and improve the stability of the PLL circuit. Based on SMIC 40 nm CMOS process, the simulation results show that the output frequency ranges from 62.5 MHz to 1500 MHz, and the PLL has a phase noise of-97.56 dBc @ 1 MHz. Meanwhile, the circuit's power consumption is 2.5 m W at the supply voltage of 1.1 V. When the output frequency is 500 MHz, the locking time of the loop is less than 2 μs.
A self-biased phase-locked-loop with high stability and low power consumption is designed. The circuit uses a single charge pump structure, and a quick start module is added at the same time. The locking time of the loop is reduced without increasing power consumption. The circuit has a fixed damping factor and the circuit parameters are determined through derivation and calculation to keep the circuit lying near the optimal point of phase margin and improve the stability of the PLL circuit. Based on SMIC 40 nm CMOS process, the simulation results show that the output frequency ranges from 62.5 MHz to 1500 MHz, and the PLL has a phase noise of-97.56 dBc @ 1 MHz. Meanwhile, the circuit's power consumption is 2.5 m W at the supply voltage of 1.1 V. When the output frequency is 500 MHz, the locking time of the loop is less than 2 μs.
引文
[1] GICRKINK S L J. Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and selfcorrecting charge pump[J]. IEEE J Sol Sta Circ, 2008,43(12):2967-2976.
[2] Dai L, Harjani R. Design of low-phase-noise CMOS ring oscillators[J]. IEEE Transactions on Circuits&Systems II Analog&Digital Signal Processing, 2015, 49(5):328-338.
[3] MANEATIS J G. Low-jitter process-independent DLL and PLL based on self-biased techniques[J]. IEEE J Sol Sta Circ, 1996, 31(11):1723-1732.
[4]范昊,黄鲁,胡腾飞.一种基于自偏置技术的低功耗锁相环设计[J].微电子学,2015, 45(02):196-199.
[5]谭茗,唐立军,黄水龙,谢海情.基于40nm CMOS工艺可快速锁定的宽带锁相环电路设计[J].微电子学与计算机, 2014, 31(01):156-159.
[6]何国军,李荣宽.电荷泵锁相环2阶无源环路滤波器的设计[J].微电子学,2015, 45(02):184-187.
[7]何乐年,王忆.模拟集成电路设计与仿真[M],科学出版社, 2008.
[8]施展,余隽,唐祯安,蔡泓,冯冲.高性能集成锁相环中低失配电荷泵的设计[J].电子与信息学报, 2017,39(06):1472-1478.
[9]李演明,仝倩,倪旭文,邱彦章,文常保,吴凯凯,柴红.一种改进型的CMOS电荷泵锁相环电路[J].半导体技术, 2014, 39(04):248-253.
[10]李琦,冯春燕,李海鸥,张法碧,陈永和,黄平奖,杨年炯.具有温度补偿的16MHz CMOS环形振荡器设计[J].半导体技术, 2017, 42(02):91-96+114.
[11]盛炜,张国华,杨霄垒,张沁枫.一种基于自偏置技术的低抖动锁相环[J].微电子学, 2017, 47(03):351-354.
[2] Dai L, Harjani R. Design of low-phase-noise CMOS ring oscillators[J]. IEEE Transactions on Circuits&Systems II Analog&Digital Signal Processing, 2015, 49(5):328-338.
[3] MANEATIS J G. Low-jitter process-independent DLL and PLL based on self-biased techniques[J]. IEEE J Sol Sta Circ, 1996, 31(11):1723-1732.
[4]范昊,黄鲁,胡腾飞.一种基于自偏置技术的低功耗锁相环设计[J].微电子学,2015, 45(02):196-199.
[5]谭茗,唐立军,黄水龙,谢海情.基于40nm CMOS工艺可快速锁定的宽带锁相环电路设计[J].微电子学与计算机, 2014, 31(01):156-159.
[6]何国军,李荣宽.电荷泵锁相环2阶无源环路滤波器的设计[J].微电子学,2015, 45(02):184-187.
[7]何乐年,王忆.模拟集成电路设计与仿真[M],科学出版社, 2008.
[8]施展,余隽,唐祯安,蔡泓,冯冲.高性能集成锁相环中低失配电荷泵的设计[J].电子与信息学报, 2017,39(06):1472-1478.
[9]李演明,仝倩,倪旭文,邱彦章,文常保,吴凯凯,柴红.一种改进型的CMOS电荷泵锁相环电路[J].半导体技术, 2014, 39(04):248-253.
[10]李琦,冯春燕,李海鸥,张法碧,陈永和,黄平奖,杨年炯.具有温度补偿的16MHz CMOS环形振荡器设计[J].半导体技术, 2017, 42(02):91-96+114.
[11]盛炜,张国华,杨霄垒,张沁枫.一种基于自偏置技术的低抖动锁相环[J].微电子学, 2017, 47(03):351-354.