一种自校准高精度时间放大器
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摘要
提出了一种应用于时间数字转换器的2倍增益自校准时间放大器。该时间放大器能动态调整支路电容的充放电时间,有效提高了增益稳定性。基于65nm CMOS工艺进行设计,电源电压为1V。仿真结果表明,在不同温度和工艺角下,动态输入范围可达600ps,增益误差小于10%。在6级级联的条件下,最小精度为0.46ps,归一化差分误差为0.15LSB,归一化绝对误差为0.19LSB。与传统时间放大器相比,该时间放大器的性能明显改善。
With 2 xtime gain self-calibration circuits,a 2 xtime amplifier(TA)applied in time-to-digital converters was designed.The time gain stability of TA was effectively improved by using self-calibration circuits to adjust the charge or discharge currents of the capacitor dynamically.Based on a 65 nm CMOS technology,the TA was designed with a supply voltage of 1 V.The simulation results showed that the dynamic input range of TA was greater than 600 ps and its gain error was less than 10% under the conditions of different temperatures and process corners.For the 6 stage cascade TA,the precision,normalized differential error(NDE)and normalized absolute error(NAE)were 0.46 ps,0.15 LSB and 0.19 LSB respectively.Consequently,the performance of the proposed TA was significantly improved compared with that of the traditional TAs.
With 2 xtime gain self-calibration circuits,a 2 xtime amplifier(TA)applied in time-to-digital converters was designed.The time gain stability of TA was effectively improved by using self-calibration circuits to adjust the charge or discharge currents of the capacitor dynamically.Based on a 65 nm CMOS technology,the TA was designed with a supply voltage of 1 V.The simulation results showed that the dynamic input range of TA was greater than 600 ps and its gain error was less than 10% under the conditions of different temperatures and process corners.For the 6 stage cascade TA,the precision,normalized differential error(NDE)and normalized absolute error(NAE)were 0.46 ps,0.15 LSB and 0.19 LSB respectively.Consequently,the performance of the proposed TA was significantly improved compared with that of the traditional TAs.
引文
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[2] DENG X,MO Y,LIN X,et al.A 0.68-to-1.44GHz low-jitter all-digital phase-locked loop with a novel PFD and a high resolution DCO in 0.18μm CMOS[C]∥IEEE Int Conf EDSSC.Hongkong,China.2016:104-107.
[3]李乾锋.基于0.18μm CMOS工艺的时间数字转换器的设计与实现[D].南京:东南大学,2015.
[4]甘武兵.基于线性增强TDC的全数字锁相环设计[D].成都:电子科技大学,2014.
[5]李大鹏,徐东明,陈文宣.基于门延时的数字TDC电路设计[J].中国集成电路,2011,20(7):37-40.
[6] HWANG C S,CHEN P,TSAO H W.A high-precision time-to-digital converter using a two-level conversion scheme[C]∥IEEE Nucl Sci Symp Conf Record.Portland,OR,USA.2004:174-176.
[7] STASZEWSKI R B,VEMULAPALLI S,VALLUR P,et al.1.3 V 20ps time-to-digital converter for frequency synthesis in 90-nm CMOS[J].IEEE Trans Circ&Syst II:Expr Bri,2006,53(3):220-224.
[8] LEE S K,SEO Y H,SUH Y,et al.A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18μm CMOS[C]∥IEEE ISSCC.San Francisco,CA,USA.2010:482-483.
[9] LEE M,ABIDI A A.A 9b,1.25ps resolution coarse-fine time-to-digital converter in 90nm CMOS that amplifies a time residue[J].IEEE J Sol Sta Circ,2008,43(4):769-777.
[10]刘晓露.全数字锁相环中的时间数字转换器研究与设计[D].上海:复旦大学,2013.
[11]DEHLAGHI B,MAGIEROWSKI S,BELOSTOTSKI L. Highly-linear time-difference amplifier with low sensitivity to process variations[J].Elec Lett,2011,47(13):743-745.
[12] MOLAEI H,KHORAMI A,HAJSADEGHI K.A wide dynamic range low power 2×time amplifier using current subtraction scheme[C]∥IEEE Int Symp Circ&Syst. Montreal, Canada. 2016:462-465.