一种12位84 dB无杂散动态范围的高精度低功耗SAR ADC
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摘要
由于穿戴设备的能量限制对ADC的功耗提出了更高的要求,所以在本设计的12位高精度低功耗SAR ADC中DAC部分采用VCM-Based电容开关时序来降低功耗;比较器部分通过在低精度模式和高精度模式间切换的方法来减少功耗,同时合理设计脉宽,降低工作时间,进一步降低功耗;SAR逻辑部分的时钟信号由比较器输出控制,减少不必要的功耗浪费,同时实现较高的无杂散动态范围。设计基于CSMC 0.18μm CMOS工艺,在1.8 V电源电压和10 k Sps的采样频率下,得到ADC的性能参数为:无杂散动态范围(SFDR)83.97 d B,信噪失真比(SNDR)71.92 d B,有效位数(ENOB)11.65 bit,总功耗868 n W,品质因数(FOM)28.6 f J/Conv,芯片面积472μm×199μm。
Due to the energy limitations of wearable equipment, the power of ADC has more strict requirements. Therefore, we proposed a 12-bit high-precision low-power SAR ADC in this work, where the capacitor array adopts VCM-Based capacitor switching timing to optimize the power consumption; the comparator switches between low-precision mode and high-precision mode to reduce power consumption, and the pulse width is reasonably designed to shorten the time of comparison and further decrease power consumption. SAR logic clock is controlled by the comparator output, reducing unnecessary waste of power,and the high spurious free dynamic range is achieved. Based on the CSMC 0.18 μm CMOS process at 1.8 V supply voltage and 10 k Sps sampling frequency: the Spurious Free Dynamic Range is 83.97 d B, the Signal to Noise and Distortion Ratio(SNDR) is 71.92 d B, the Effective Number of Bits(ENOB) is 11.65 bit, the total power consumption is 868 n W and Figure of Merit(FOM) is 28.6 f J/Conv, the chip area is 472 μm×199 μm.
Due to the energy limitations of wearable equipment, the power of ADC has more strict requirements. Therefore, we proposed a 12-bit high-precision low-power SAR ADC in this work, where the capacitor array adopts VCM-Based capacitor switching timing to optimize the power consumption; the comparator switches between low-precision mode and high-precision mode to reduce power consumption, and the pulse width is reasonably designed to shorten the time of comparison and further decrease power consumption. SAR logic clock is controlled by the comparator output, reducing unnecessary waste of power,and the high spurious free dynamic range is achieved. Based on the CSMC 0.18 μm CMOS process at 1.8 V supply voltage and 10 k Sps sampling frequency: the Spurious Free Dynamic Range is 83.97 d B, the Signal to Noise and Distortion Ratio(SNDR) is 71.92 d B, the Effective Number of Bits(ENOB) is 11.65 bit, the total power consumption is 868 n W and Figure of Merit(FOM) is 28.6 f J/Conv, the chip area is 472 μm×199 μm.
引文
[1]Mccreary J L,Gray P R.All-MOS charge redistribution analog-to digital conversion techniques Part-I[J].IEEE Journal of Solid-State Circuits,SC-10(6),371-379.IEEE Journal of Solid-State Circuits,1976,10(6):371-379.
[2]Alhawari M,Albelooshi N,Perrott M H.A 0.5V<4μW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer[C]//IEEE Solid-State Circuits Conference Digest of Technical Papers,2013:384-385.
[3]Pamula V R,Valero-Sarmiento J M,Long Y,et al.A 172μW Compressively Sampled Photoplethysmographic(PPG)Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data[J].IEEE Transactions on Biomedical Circuits&Systems,2017,11(3):487-496.
[4]Wang Q,Zhou L,Peng Z,et al.A 12-b 100MS/s low-power successive approximation register ADC in 65 nm COMS[C]//IEEE International Conference on Electron Devices and Solid-State Circuits.IEEE,2015:1-2.
[5]Liu S,Shen Y,Zhu Z.A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching[J].IEEE Transactions on Circuits&Systems I Regular Papers,2016,63(10):1616-1627.
[6]Gudlavalleti R H,Bose S C.Ultra low power 12-Bit SAR ADC for wireless sensing applications[C]//IEEE International Conference on VLSI Systems,Architectures,Technology and Applications,2016:1-4.
[7]Naveen I G,Sonoli S.Design and simulation of 10-bit SAR ADC for low power applications using 180 nm technology[C]//IEEE International Conference on Electrical,Electronics,Communication,Computer and Optimization Techniques,2016:331-335.
[8]Verma N,Chandrakasan A P.An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes[J].IEEE Journal of Solid-State Circuits,2007,42(6):1196-1205.
[9]Zeng Z,Dong C S,Tan X.A 10-bit 1MS/s low power SAR ADC for RSSI application[C]//IEEE International Conference on Solid-State and Integrated Circuit Technology,2010:569-571.
[10]Tang H,Sun Z C,Chew K W R.A 5.8 n W 9.1-ENOB1-k S/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device[J].IEEE Transactions on Very Large Scale Integration Systems,2014,22(10):2221-2225.
[11]Zhang D,Bhide A,Alvandpour A.A 53-n W 9.1-ENOB1-k S/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices[J].IEEE Journal of Solid-State Circuits,2012,47(7):1585-1593.
[2]Alhawari M,Albelooshi N,Perrott M H.A 0.5V<4μW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer[C]//IEEE Solid-State Circuits Conference Digest of Technical Papers,2013:384-385.
[3]Pamula V R,Valero-Sarmiento J M,Long Y,et al.A 172μW Compressively Sampled Photoplethysmographic(PPG)Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data[J].IEEE Transactions on Biomedical Circuits&Systems,2017,11(3):487-496.
[4]Wang Q,Zhou L,Peng Z,et al.A 12-b 100MS/s low-power successive approximation register ADC in 65 nm COMS[C]//IEEE International Conference on Electron Devices and Solid-State Circuits.IEEE,2015:1-2.
[5]Liu S,Shen Y,Zhu Z.A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching[J].IEEE Transactions on Circuits&Systems I Regular Papers,2016,63(10):1616-1627.
[6]Gudlavalleti R H,Bose S C.Ultra low power 12-Bit SAR ADC for wireless sensing applications[C]//IEEE International Conference on VLSI Systems,Architectures,Technology and Applications,2016:1-4.
[7]Naveen I G,Sonoli S.Design and simulation of 10-bit SAR ADC for low power applications using 180 nm technology[C]//IEEE International Conference on Electrical,Electronics,Communication,Computer and Optimization Techniques,2016:331-335.
[8]Verma N,Chandrakasan A P.An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes[J].IEEE Journal of Solid-State Circuits,2007,42(6):1196-1205.
[9]Zeng Z,Dong C S,Tan X.A 10-bit 1MS/s low power SAR ADC for RSSI application[C]//IEEE International Conference on Solid-State and Integrated Circuit Technology,2010:569-571.
[10]Tang H,Sun Z C,Chew K W R.A 5.8 n W 9.1-ENOB1-k S/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device[J].IEEE Transactions on Very Large Scale Integration Systems,2014,22(10):2221-2225.
[11]Zhang D,Bhide A,Alvandpour A.A 53-n W 9.1-ENOB1-k S/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices[J].IEEE Journal of Solid-State Circuits,2012,47(7):1585-1593.