低电容TVS二极管外延技术研究
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摘要
低电容瞬态电压抑制器(TVS)是用来保护高频电路电压瞬变和浪涌防护的半导体器件,通过在重掺杂的P型掺硼衬底上生长近似本征的高阻N型外延层形成低电容导引二极管。高阻N型外延生长过程中的自掺杂现象特别严重,是产品量产面临的重大挑战。通过优化衬底背封工艺,采用外延缓冲层,结合高温烘烤,低温变速赶气等技术,从而在重掺杂P型衬底上生长出满足生产需要的高阻N型外延层,得到的器件电容及漏电均达到要求,产品良率达到98%以上。
In the conventional manufacturing of low capacity TVS(Transient Voltage Suppressor) semiconductors(known for their use in circuit protection in the event of electrostatic discharge, quick transients, and electrical surges), the low capacity diode of TVS device requires a layer of high resistivity N-type epitaxial layer to be deposited on a heavily doped P-type substrate. The deposition of this N-type layer presents a particular challenge with respect to aut-doping effect. In this paper, the auto-doping from P-type substrate was effectively suppressed through a combination of back sealing optimization, buffered Epitaxial layer growth, etc. In addition, a high temperature bake and low temperature periodic variable speed H2 purges were carried out before performing the high resistivity Epitaxial layer deposition. A high resistivity(>150 Ω cm) N-type Epitaxial film was eventually deposited and the TVS device was successfully mass produced in an eight-inch production environment. Both the capacity and leakage of the TVS device meet the request.
In the conventional manufacturing of low capacity TVS(Transient Voltage Suppressor) semiconductors(known for their use in circuit protection in the event of electrostatic discharge, quick transients, and electrical surges), the low capacity diode of TVS device requires a layer of high resistivity N-type epitaxial layer to be deposited on a heavily doped P-type substrate. The deposition of this N-type layer presents a particular challenge with respect to aut-doping effect. In this paper, the auto-doping from P-type substrate was effectively suppressed through a combination of back sealing optimization, buffered Epitaxial layer growth, etc. In addition, a high temperature bake and low temperature periodic variable speed H2 purges were carried out before performing the high resistivity Epitaxial layer deposition. A high resistivity(>150 Ω cm) N-type Epitaxial film was eventually deposited and the TVS device was successfully mass produced in an eight-inch production environment. Both the capacity and leakage of the TVS device meet the request.
引文
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[2]TOKIN C.High Resistance Epitaxial layer formation method in Semiconductor device manufacture–involves forming high resitnce Epitaxial layer on upper surface of silicon wafer,after forming back seal epitaxial layer on backside of silicon wafer[P].Japan:JP 10064826-A,1998.
[3]张关保,苏海伟,李星等.集成低压TVS器件及其制作方法[P].China:CN 101527304A,2009.
[4]张常军,李昕华,陈向东.超低电容瞬态电压抑制器件及其制造方法[P].China:CN102437156 A,2012.
[5]纪纲,顾建平.TVS二极管及其制作方法[P].China:CN 103050545 A,2013.
[6]朱伟东,吴昊,赵泊然.低电容超深沟槽瞬变电压抑制二极管结构[P].China:CN103208530 A,2013.
[7]高涛,谭卫东,马利行P型重掺衬底高阻厚层硅外延技术研究[C].第十四届全国半导体集成电路、硅材料学术会议.中国珠海,2005:324–326.
[8]刘玉岭,金杰,徐晓辉等.硅CVD外延自掺杂效应的分析研究[J].电子科学,1996,18(3):332–336.
[9]刘玉岭,檀柏梅.提高P型硅外延电阻率一致性的控制方法[P].China:CN1870219A,2006.
[10]王向武,陆春一,赵仲镛.改进的二步法生长双层、异型硅外延材料[J].固体电子学研究与进展,1994,14(1):75–79.
[11]王向武,陆春一.多层硅外延中自掺杂现象研究[J].固体电子学研究与进展,1994,14(3):267–271.
[12]谭卫东.4英寸P/p+高阻厚层外延片电阻率的精确控制[C].第十二届全国半导体集成电路和硅材料学术会议.中国广州,2001:10–13.
[13]谭卫东,唐有青,马利行等.低阻P型衬底上高阻厚层n型外延[J].半导体学报,2006,12(27):183–185.
[14]袁肇秋,魏毓峰.200mm高阻厚层Si外延技术研究[J].半导体技术,2008,33(5):391–394.