摘要
电子稳像技术是一种视频图像序列稳定技术,它是直接利用图像信息来检测图像的位移矢量,然后通过运动补偿以获取清晰稳定的视频序列。它广泛应用于军事领域和民用领域。
本文主要介绍了电子稳像的基本原理及常用算法,对常用算法灰度投影算法、位平面匹配算法、代表点匹配算法和特征点匹配算法的实现流程和优缺点进行详细介绍,并对运动补偿的方法进行了简要概括。本文着重介绍的是电子稳像系统在FPGA开发平台上的实现方法,将系统分为视频采集、视频缓存、视频稳像和视频输出四个模块来一一介绍。在实现过程中解决了跨时钟域的同步问题,视频序列大数据量的缓存问题,以及运动估计算法和运动补偿在FPGA上的实现等问题。本论文根据稳像系统综合后的RTL原理图来对系统的各个模块在FPGA上的实现方法进行详细介绍,并对各个模块的综合与仿真结果进行了详细介绍。
本文的电子稳像系统在Seed Fem025开发平台进行设计,应用Xilinx提供的ISE软件进行综合与仿真,采用Verilog HDL硬件描述语言对系统进行设计,并对系统中各模块的实现作了综合与仿真工作,并在FPGA开发板上进行了下载验证。本课题完成了对系统各个模块及整个系统的功能验证工作。
Electronic image stabilization technology is a video image sequence stabilized technique, it makes use of the image information to detect the displacement vector of the image, and then through motion compensation to obtain a clear and stable video sequence. It is widely used in military and civilian fields.
In this dissertation, the basic principles for electronic image stabilization and the commonly used image stabilization algorithms are introduced, and but only details the implementation process, the advantages and disadvantages of gray projection algorithm, bit plane matching algorithm, the representative point matching algorithm and feature point matching algorithm, and also briefly summarize the motion compensation methods.The dissertation focuses on the implementation of the electronic image stabilization system on the FPGA development platform, and the system can be divided into four modules: video capture, video caching, video stabilization and video output. In this system, the problems that how to synchronize the cross-clock, to cache the large amount of video sequences, to implement the motion estimation and motion compensation on the FPGA development platform have been solved. According to the RTL schematic of image stabilization system simulated by ISE, the article details the implementation of each module on the FPGA platform, and details these synthesis and simulation results.
In this dissertation, the electronic image stabilization system is designed in the platform of Seed Fem025, using ISE to synthesize and simulate the design, and make use of Verilog HDL to describe the system architecture, and synthesis and simulation for each module has been done. This dissertation finished the system function verification.
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