摘要
过去十多年里,数字视频技术被广泛地应用于计算机、通信、广播和电视领域,带来了电视会议、可视电话、数字电视等一系列新型应用。近些年,随着数字音视频编解码技术和超大规模集成电路的发展,以AVS和H.264/AVC为代表的新一代视频编码标准成为主流。AVS和H.264/AVC视频编码标准采用了最新的视频编码技术,获得了很好的效果,但是其压缩效率的提高是以压缩算法复杂度的提高为代价的。这使得单纯用软件来实现解码,难以达到实时,尤其是高清晰度电视,必须通过硬件电路加速解码才能实现高清实时,综合考虑,专用集成电路(ASIC)设计是解码器的最佳实现方案。
本文通过研究AVS和H.264/AVC视频编解码标准,归纳了两种标准中视频编解码算法的异同点,说明了两种标准复用的可行性。在此基础上,通过软硬件的划分方法提出了一种同时支持AVS和H.264/AVC的视频解码器系统设计方案,并通过并行设计和数据流驱动等先进设计方法上对解码器硬件模块进行了合理的划分。本文对AVS和H.264/AVC多标准可配置的视频解码器的研究,有助于我国AVS高清视频编解码芯片的开发,并且有助于AVS标准产业化。
为了进一步在多个领域推广AVS标准,并提高多模解码器的灵活性,本文还对解码器的输出模块(Display Feeder,DF)做了深入的研究,进而提出了DF多路并行输出的硬件结构,这种结构采用高效的片外帧缓存和片上三级缓存的方法,使得片外存储器数据带宽减少25%且数据读取速率提高将近三倍,解码器可以输出多个图像给一个监视器,还可以输出多个图像给多个监视器显示。本设计通过Verilog HDL语言加以实现,通过了Modelsim的仿真,并在FPGA上通过了验证,通过高清电视的直观显示,可以证明本设计的正确性,并说明多模视频解码器还可以进一步应用到数字视频监控领域。
In the past ten years,digital video technology has been widely used in field of computer,communication,TV,broadcast,which has brought a series of new applications such as TV conference,videophone,digital TV and so on.In recent years, with the development of digital audio video codec technique and VLSI,AVS and H.264/AVC have represented a new generation of video coding standard and become to be the mainstream.By introducing the latest video coding technology,AVS and H.264/AVC gain a wonderful coding efficiency.However,the improvement of compression efficiency is based on the cost of the complexity of compression algorithm.For high-definition television,it is difficult to achieve real-time by software decoding.That makes it is difficult to achieve real-time decoding only by software.Especially high-definition television,hardware accelerator or appropriative hardware decoding circuit is necessary.Considering above situation,ASIC implementation is the best program for decoder design.
By investigating AVS and H.264/AVC standards,similarities and differences about algorithm of two standards are summarized in the thesis.Furthermore,system design scheme of multi-mode decoder is proposed through the way of Hardware/Software Partitioning,and reasonable hardware modules partitioning is carried out through the way of advanced design methods,such as parallel design,data drive technique and so on.The research on multi-standard and configurable video decoder is helpful for the design of AVS SDTV/HDTV video codec chip and for the industrialization of AVS standard consequently.
In order to improve decoder flexibility and promote AVS standards to more fields, the thesis also makes a deep research on decoder output module DF and proposes the hardware architecture for multi-channel parallel output.This architecture adopts an efficient method for multi-channel parallel frame buffer and three-level buffer-on-chip,which can reduce 25%of memory data bandwidth and improve nearly three times of reading speed.The decoder can output a number of pictures onto a monitor,or onto several monitors.DF design is implemented by Verilog HDL, simulated by Modelsim and successfully verified on Altera FPGA verification board. The multi-channel pictures are displayed on the high-definition television can prove this design functional correctness.So the multi-mode decoder with new DF design can be applied to the field of digital video monitor.
引文
[1]http://www.chiariglione.org/mpeg/
[2]http://www.itu.int
[3]http://www.avs.org.cn
[4]数字音视频编码技术标准工作组.信息技术先进音视频编码 第2部分:视频(GB/T 200090.2-2006).中国国家标准化管理委员会,2006
[5]Intel Embedded Pentium Processor with MMX Technology Datasheet.ftp://download.intel.com/design/intarch/datashts/27321401.pdf
[6]R.Gerber,A.J.C.Bik,K.B.Smith,X.Tian.The Software Optimization Cookbook,Second Edition.Intel Press.
[7]S.Oberman,G.Favor,F.Weber.AMD 3DNow! Technology:Architecture and Implementations.IEEE Micro,1999,19(2):37～48
[8]M.Tremblay,J.M.O'Connor.UltraSparc I:A Four-Issue Processor Supporting Multimedia.IEEE Micro,1996,16(2):42～50
[9]K.Diefendorff,P.K.Dubey,R.Hochsprung,H.Scale.AltiVec Extension to PowerPC Accelerates Media Processing.IEEE Micro,2000,20(2):85～95
[10]Texas Instruments Incorporated.TMS320DM6446 Digital Media System-on-Chip,2006,http://www.ti.com
[11]S.W.Wang,Y.T.Yang et al.The Optimization of H.264/AVC Baseline Decoder on Low-cost TriMedia DSP Preocessor.Proceedings of the SPIE,Denver,Colorado,USA,2004,5558:524～535
[12]敖行.基于DSP的实时视频压缩系统的开发.中国有线电视.2004,(1):55～56
[13]58 H.Mizosoe,K.Maeda,Y.Kubo,Y.Tsuru,K.Koruki.An Advanced Multimedia Processing LSI Suitable for HDTV Applications.Proceedings of 2001 International Conference on Consumer Electronics,2001:96～97
[14]H.Yamauchi,S.Okada,K.Taketa,Y.Matsuda,T.Mori.A 0.8W HDTV Video Processor with Simultaneous Decoding of Two MPEG2 MP@ML Streams and Capable of 30frames/s Reverse Playback.Proceedings of 2002 Conference on International Solid-State Circuits,2002:473～474
[15]H.Yamauchi,S.Okada,K.Taketa,Y.Mihara,Y.Harada.Single Chip Video Processor for Digital HDTV.IEEE Transactions on Consumer Electronics,2001,47(3):394～404
[16]H.Arakida,M.Takahashi,Y.Tsuboi et al.A 160mW,80nA Standby,MPEG-4Audiovisual LSI with 16Mb Embedded DRAM and a 5GOPS Adaptive Post Filter.Proceedings of 2003 IEEE International Solid-State Circuits Conference,2003:266～267
[17]Himanshu Bhatnagar,Advanced ASIC Chip Synthesis,Kluwer Academic Publishers,2002
[18]黄铁军,高文,“AVS实现重大系统集成创新”,中国科学院院刊,2005,20(4):301-304
[19]ITU-T.Video Codec for Audiovisual Services at px64 kbit/s.ITU-T Rec.H.261,1993
[20]ITU-T,ISO/IEC JTC1/SC29/WG11.Information Technology-Generic Coding of Moving Pictures and Associated Audio Information-Part 2:Video,ITU-T Rec.H.262|ISO/IEC 13818-2,1994
[21]ITU-T.Video Coding for Low Bit Rate Communication.ITU-T Rec.H.263Version 1,1993
[22]Joint Video Team(JVT) of ISO/IEC MPEG and ITU-T VCEG.Advanced Video Coding for Generic Audiovisual Services.ITU-T Rec.H.264 |ISO/IEC 14496-10AVC,2003
[23]ISO/IEC JTC1/SC29/WG11.Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5Mbit/s -Part 2:Video,ISO/IEC 11172-2,1993
[24]ISO/IEC 14496-2,Information Technology-Coding of Audio-Visual Objects:Part 2-Visual,January 2001
[25]ISO/IEC JTC1/SC29/WG11.Information Technology-Coding of Audio-Visual Objects-Part 2:Visual,ISO/IEC 14496-2,1999
[26]ITU-T.Video Coding for Low Bit Rate Communication.ITU-T Rec.H.263Version 2,1997
[27]ITU-T.Video Coding for Low Bit Rate Communication.ITU-T Rec.H.263Version 3,200
[28]D.Wu,W.Gao,M.Z.Hu,and Z.Z.Ji.A VLSI Architecture Design of CAVLC Decoder.Proceedings of IEEE International Conference on ASIC,2003,2:21～24
[29]D.Marpe,H.Schwarz,and T.Wiegand.Context-based Adaptive Binary Arithmetic Coding in the H.264/AVC Video Compression Standard.IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7):620～636
[30]N.Zhang,B.C.Yin,D.H.Kong,W.Y.Yue.Spatial Prediction Based Intra-Coding.Proceedings of 2004 IEEE International Conference on Multimedia and Expo,Taipei,2004,1:97～100
[31]S.W.Ma,W.Gao,X.P.Fan.Low Complexity Integer Transform and High Definition Coding.Proceedings of the SPIE,Denver,Colorado,USA,2004,5558:547～554
[32]Q.Wang,D.B.Zhao,S.W.Ma,Y.Lu,Q.M.Huang,W.Gao.Context-Based 2D-VLC for Video Coding.Proceedings of 2004 IEEE International Conference on Multimedia and Expo,Taipei,2004,1:89～92
[33]毕厚杰,新一代视频压缩编码标准--H.264/AVC,人民邮电出版社,2005
[34]楼剑,虞露。浙江大学通信与信息工程研究所,AVS 8×8整数变换的改进,AVS_M1101,2003.7
[35]楼剑,虞露。浙江大学通信与信息工程研究所,量化的改进,AVS_M1151,2003.10
[36]Huizhu Jia,Peng Zhang,Don Xie,et al.An AVS HDTV Video Decoder Architecture Employing Efficient HW/SW Partitioning[J].IEEE Transactions on Consumer Electronics,2006,52(4)
[37]G.Stitt,F.Vahid,G.McGregor,B.Einloth,"Hardware/software Partitioning of Software Binaries:A Case Study of H.264 Decode",Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis,pp.285-290,2005
[38]吴艳芳,嵌入数字电视机顶盒中的解复用器实现,计算机与数字工程,2006,34(12)
[39]屠颖尊,解光军,黄晁,用于AVS和H.264可变长解码器的设计与实现,集成电路应用,2006.1
[40]杨意仲,张申科等,H.264及AVS视频解码器中IQ╱IDCT的设计与实现,电子技术应用,2007.3
[41]谢朝辉,冯燕等,H.264和AVS多模视频解码器中运动矢量预测的硬件实现,微电子学与计算机,2006,23(11)
[42]张伟,王晓阳等,一种快速的H.264到AVS帧内模式决策算法,电视技术,2007.9
[43]冯燕,刘肃,谢朝辉,“视频解码芯片中去块效应环路滤波的硬件实现”,计算机工程,2007:33(7)
[44]孙宁,叶兵等,H.264及AVS高清视频解码中SDRAM控制器的设计与实现,微电子学与计算机,2007,24(1)
[45]Michael Keating,David Flynn,Robert Aitken,Alan Gibbons,Kaijian Shi," Low Power Methodology Manual For System-On Chip Design",Springer,ISBN:978-0-387-71818-7
[46]Recommendation ITU-R BT.656-4,level of recommendation ITU-R BT.601[S].1998
[47]Data Sheet of ADV7302A/ADV7303A,http://www.analog.com
[48]The I2C-BUS Specification/Data Sheet.Philips 2000
[49]Recommendation ITU-R BT.1120-5,digital interfaces for HDTV studio signals [S].2004
[50]Data Sheet of HYB25D128160CE-5,Published by Infineon Technologies AG,2005-11
[51]Stefans Sjoholm,Lennart Lindh,"The Need for Co-simulation in ASIC-verification" Proceedings of the 23rd EUROMICRO Conference,pp.331-335,Budapest Hungary,September 1997
[52]www.altera.com
[53]StratixⅡ Device Handbook,Altera Corporation,2005-12
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