摘要
横向双扩散MOS晶体管LDMOS(Lateral Double-diffused MOS transistors)因性能、价格和易于集成等优势,在智能功率集成电路SPIC(Smart Power IntegratedCircuits)中被广泛应用,常作为功率开关器件。随着微电子技术的发展,LDMOS的可靠性成为影响SPIC性能和寿命的关键问题之一。LDMOS器件通常在交流电条件下工作,根据脉冲个数的多少,交流电又可分为正常开关工作的多脉冲和不期望的异常瞬态单脉冲。一方面,在正常开关工作过程中,LDMOS器件自身的电功耗会引起自热现象,器件或SPIC的局部温度会上升;另一方面,当异常的瞬态大电流或高电压单脉冲来临时,例如静电放电ESD(Electro Static Discharge)或过度电应力EOS(Electro Over Stress)脉冲来临时,若LDMOS器件自身泄放静电的ESD能力或抗过度电应力的EOS能力过低,也会发生自热现象,器件或SPIC的局部温度也会急剧上升。如果温度上升过高,就可能引发多晶硅或金属连线的烧毁、器件的热二次击穿、甚至硅片管芯的熔化等严重后果。另外,温度升高也会引发器件本身或周边低压电路的性能发生变化。因此,LDMOS器件的温度特性是关系器件或SPIC热安全工作和可靠性方面的重要问题。
本论文正是针对上述问题,在充分了解国内外功率器件电热效应和静电放电方面研究现状的基础上,以通常用于SPIC的40V-LDMOS器件为例,重点研究在正常开关模式(重复多脉冲)和异常ESD/EOS(瞬态单脉冲)情况下工作时LDMOS器件内部的电热效应和温度特性,深入分析其物理机制,得到一系列的结论,这些结论可以为深入研究和改善功率器件的可靠性和热安全工作区提供参考。
本文的独创性工作主要表现在第三章、第四章、第五章和第六章,主要内容为:
1,利用LDMOS器件的等效热路模型得到器件在外加交流电作用下的温度表达式,并阐述公式所描述的物理意义。在单脉冲作用下器件升温公式的基础上,本文提出单脉冲作用下的降温公式和多脉冲作用下的温度公式,并对照实验结果给予证明和分析。器件内部的温度与初始温度、热特性(热阻和热容等)、外加的电脉冲等参数密切相关。当器件在多脉冲下工作时,温度会发生周期性的“升温、降温、升温”的过程,该过程可以用稳态响应或暂态响应来描述。
2,研究LDMOS器件在交流电下工作时器件内部的最高温度与工作频率之间的关系,给出较低频率和较高频率下最高温度的表达式。在不同频率下,影响器件温度的参数是不一样的,因此为令器件工作在热安全区,需要调整和优化的参数是随着工作频率而变化的。在较低频率下工作时,最高温度是热阻、热容、功耗、占空比、周期的函数;在较高频率下工作时,器件会处于“一直升温”状态,此时热阻和周期的影响作用将消失,而热容和连续工作时间却成为影响器件温度的主要因素,并给出一定的实验结果予以证明。
3,研究栅接地LDMOS(Gate-Grounded LDMOS)器件在关断期间,瞬态大电流单脉冲来临时(如ESD脉冲)器件内部发生的电热效应和物理机制。当器件工作在ESD大电流区时,其内部寄生NPN晶体管触发导通,用等温分析方法和电热分析方法得到的输出特性是不同的,本文给出原因分析,并分析温度的分布和温度弛豫时间对漏极电压弛豫时间的影响。电热分析方法既可更准确预测器件的输出特性,还可预测热击穿发生的位置。
4,研究栅耦合LDMOS(Gate-Coupled LDMOS)器件在正常导通期间,瞬态大电流单脉冲来临时(如ESD脉冲)器件内部发生的电热效应和物理机制。同栅接地相比,正栅压相当于增加寄生NPN管发射极的注入效率,有源区的电流密度、功率密度和温度增加,不利于器件在ESD大电流区工作;而负栅压相当于降低寄生NPN管发射极的注入效率,有源区的电流密度、功率密度和温度减少,利于器件在ESD大电流区工作。
LDMOS (Lateral Double-diffused MOS transistors) power devices are widely used as output drivers in switching modes in SPIC (Smart Power Integrated Circuits) because of their low cost and specific performances. It is significant that the reliabilities of LDMOS devices play a more and more important role responsible for the reliabilities and life-span of both themselves and SPIC with the development of micro-electronics technology. LDMOS devices often operate under DC (Direct Current) or AC (Alternating Current) conditions, where AC includes continuous multi-pulses and the ultra transient single pulse such as ESD (Electro Static Discharge) and EOS (Electro Over Stress). When LDMOS devices operate in switching modes under continuous pulses of applied electric power, the self-heating effects induced by power dissipation occurs and the temperature will fluctuate within the devices. When LDMOS devices operate in self-protecting modes under the ultra transient single pulse such as ESD protection, the ultra transient high current passes through gate-grounded or gate-coupled LDMOS devices and the thermal runaway will often happen. However, LDMOS devices often show a very small thermal safe operation area and striking ESD/EOS vulnerability. If the maximum temperature of LDMOS is beyond the rated range, LDMOS devices will fail and thermally break down, and wires will burn away in SPIC, and other transistors and circuits nearby will degrade, and even chips will melt. It will be especially useful to understand the responsible mechanisms in order to optimize the thermal safe operation area. Therefore, the lattice temperature of LDMOS devices is an important issue.
In this thesis, the basic responsible physical mechanisms of electro-thermal effects and temperature characteristics mentioned-above have been explored and analyzed for 40V-LDMOS power devices. Then the main results are investigated and veritified which correspond to both switching mode during continuous applied pulses and ultra high voltage/current stress during a single unexpected transient pulse such as ESD conditions. The results given here can be used as a criterion for design the thermal safe operation condition of power devices.
The author's original main work is summarized as follows, especially in Chapter 3, Chapter 4, Chapter 5 and Chapter 6.
Firstly, the specific temperature formulas are given and verified to describe periodical characteristics of lattice temperature of LDMOS devices during both continuous multi-pulses and a single pulse of applied electric power with equal thermal circuits, and the rise and fall processes of temperature during a single pulse is described in detail. There are many parameters responsible for the lattice temperature of LDMOS devices such as the initialization, thermal characteristics including thermal resistance and thermal capacitance, the details of applied pulses. Under continuous pulses LDMOS devices will have the periodical rise and fall processes of temperature, then transient response and steady response of lattice temperature are proposed and analysied.
Secondly, the relation between the maximum temperature and the switching conditions of LDMOS devices under different frequencies is studied. The results show that the maximum temperature in the device depends on the thermal capacitance, the power dissipation, the duty circle and the time of continuous operating under a high switching frequency. Whereas under a low switching frequency, the maximum temperature not only depends on those four parameters, but also depends on the thermal resistance and the period of the cycle.
Thirdly, the electro-thermal effects of GG-LDMOS (Gate-Grounded LDMOS) under ESD stress are studied. Under ESD stress the intrinsic bipolar transistor will operate. The different output characteristics of GG-LDMOS's intrinsic bipolar transistors by the isothermal and non-isothermal methods are compared and analyzed. The space distribution characteristics of GG-LDMOS are described and the influence of delay time of lattice temperature on delay time of drain voltage is proposed. It is shown that the results of the non-isothermal method are more consistent with experimental data than those of the isothermal method. With the non-isothermal method, the better output characteristics of GG-LDMOS can be gained, and the location where thermal failure will occur can be estimated.
Fourthly, the electro-thermal effects of GC-LDMOS (Gate-Coupled LDMOS) under ESD stress are studied. The influence of gate voltages on temperature of GC-LDMOS under ultra-high transient currents is studied. In comparison with gate-grounded conditions, the temperature in the device rises when gate voltages are positive which add the injection efficiency of electrons in intrinsic bipolar transistor, and that the temperature falls when gate voltages are negative which reduce the injection efficiency of electrons in intrinsic bipolar transistor. The distributions of electric fields, conduction currents and dissipated power densities under different gate voltages are investigated and compared. It is proved that positive gate voltages weaken the ESD capability of GC-LDMOS, and that negative gate voltages enhance the ESD capability.
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