摘要
微电子技术飞速进步,工艺特征尺寸已经减小到了130纳米以下,65纳米工艺已成为成熟工艺。基于集成电路工艺技术的提升,微处理器不断地更新换代,性能迅速提高。微处理器要达到高的速度,算术逻辑部件的速度必须足够快。
本文设计实现的64位1GHz整数算术逻辑部件是X流处理器中的重要运算部件之一,主体半定制实现,关键路径上的关键部件采用全定制设计实现,在没有增加过多设计时间和工作量的前提下,使设计性能从原来的500MHz提高到了1GHz。并且较好地解决了设计规模大与设计性能不高的矛盾,具有广泛的应用价值和重要的实践意义。论文的主要工作包括:
一、优化设计实现64位GHz级整数算术逻辑运算部件,采用130纳米工艺,半定制与全定制混合设计,半定制设计部分组合逻辑综合延时550ps以下,采用静态互补CMOS电路结构的全定制64位加法器版图后模拟延时730ps,采用静态传输门阵列结构的全定制64位漏斗移位网络版图后模拟延时270ps,均达到设计要求。
二、研究了高速逻辑优化设计方法,对高速逻辑优化设计流程做了描述,对逻辑级数确定、电路结构选择、前后端设计交互、全定制设计等方面提出了补充建议,对设计中需要注意的问题进行了总结,给出了解决办法。并在64位GHz整数算术逻辑运算部件的优化设计中进行了实践。
三、对层次化全定制设计和验证进行了深入研究,从设计、优化、验证三个方面层次化设计全定制模块,在电路功能验证使用形式化静态验证方法验证电路功能与设计需求一致,版图后时序模拟验证使用静态时序分析的方法辅助确定全定制设计关键路径。在工程中实践了层次化全定制设计流程,提高了验证效率,加快了全定制设计周期。
As the technology is making progress rapidly in microelectronics, the feature size has reduced below 130nm, and the 65nm process has been in practical use. Thanks to the continuous improvement of integrated circuit technology, microprocessors are developing generation after generation, and the performance is improved rapidly. The speed of Arithmetic Logic Unit must be fast enough to design high performance microprocessors.
In this thesis, a 64-bit GHz integer ALU is designed for steam processor X. A Semi-custom methodology based on standard cell is employed for the design of the main part, while the optimization of critical data-path is designed with a full-custom method. Without consuming too much time and labor, this design method improves the performance of the ALU from 500MHz to 1GHz, and it also solves the contradiction between large design scale and high performance in a better way. This 1GHz ALU design is practically applicable in a wide range of circumstance. This thesis mainly contributes to the following aspect:
1 Optimization of the 64-bit 1GHz integer ALU, using a 130nm process, both the semi-custom and full-custom design parts meet with requirements. In typical case, delay of the semi-custom design parts is below 550ps. In full-custom parts, the layout of critical paths of 64-bit adder with static CMOS circuit have a delay of about 730ps, 270ps is the largest delay in the network of 64-bit funnel shifter which is constructed with static transmission gate arry.
2 The high-speed logic design and optimization methodology is well studied, and some promotion are proposed in the design flow. Decision of logic levels, practical advices are brought out for circuit architecture chosen, parasitic feedback into tuning, full-custom design, and solutions for frequent problems in ALU design are presented. Finally, the optimization design methodology is made a practice in the optimization of 64-bit GHz integer ALU.
3 A hierarchical full-custom design and verification methodology is well studied, which carry out the full-custom design and verification hierarchically in three aspects: design, optimization and verification. Static formal verification method was used to verify circuit function and RTL description. Static timing analysis after layout is used to help finding out the critical path in the design. The methodology improves the verification efficiency and speed up the full-custom design cycle.
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