摘要
随着集成电路工艺的快速发展以及集成度的不断提高,功耗问题受到越来越多的重视。传统CMOS电路的功耗主要包括动态功耗和静态功耗。绝热电路重复利用电路中的能量,可以有效减少电路中的动态功耗。随着工艺尺寸不断地减小,在深亚微米工艺下,由漏电流产生的静态功耗在电路总功耗中所占的比重越来越大。本文选取数字系统中的重要部件存储器作为研究对象,从动态功耗和静态功耗两方面探索低功耗存储器设计。
对于存储器电路中的动态功耗,首先使用单相绝热CAL(Clocked Adiabatic Logic)电路结构设计了SRAM(Static Random Access Memory)和CAM(Content Addressable Memory)电路,作为比较,设计了传统CMOS电路结构的SRAM和CAM,通过HSPICE仿真结果显示,采用单相绝热CAL技术能有效减小SRAM和CAM电路的功耗。然后在TSMC 0.18um工艺下绘制了SRAM电路的版图,从版图级验证了单相绝热CAL SRAM电路的低功耗效果。
针对单相绝热SRAM电路的静态功耗,本文作了重点的研究。对于CAL SRAM电路在休眠状态下的漏功耗,首先在功控开关电路中应用了多阈值技术,设计了功控多阈值开关来减少CAL SRAM在休眠状态外围电路的漏功耗,然后又设计了呆滞快取技术来减少CAL SRAM核心单元电路在休眠状态下的漏功耗。对于CAL SRAM电路在工作状态下的漏功耗,本文使用双阈值技术和沟道长度偏置技术来降低。运用上述漏功耗减少技术的SRAM电路均经过HSPICE仿真验证,仿真结果显示所设计的SRAM电路的漏功耗减少效果明显。
近阈值技术可以应用在性能和频率比较低的电路中,大幅度降低这些电路的功耗。本文将近阈值技术应用到SRAM电路中,并找出SRAM电路在不同电压下的最大工作频率以及最小能量延迟积。
With the rapid development of integrated circuit process and the continuous improvement of integration, the power consumption by more and more attention. The main source of power consumption in traditional CMOS circuits is dynamic power and static power consumption. Adiabatic circuits recycle the energy of integrated circuit, which can effectively reduce the dynamic power consumption. As process geometries continue to decrease, in the deep sub-micron process, the static power consumption generated by the leakage current in the total proportion is growing. This paper selects memory as the research object, which is an important component in digital system, to design low-power memory both in dynamic power consumption and static power consumption aspects.
For the dynamic power consumption in the memory circuit, the first to use single-phase adiabatic CAL (Clocked Adiabatic Logic) circuit to design SRAM (Static Random Access Memory) and CAM (Content Addressable Memory) circuit, for comparison, the structure of traditional CMOS SRAM and CAM also be designed. By HSPICE simulation results show that single-phase adiabatic CAL logic circuit can effectively reduce power consumption of the SRAM and CAM circuit. Then to draw layout of SRAM circuit in the TSMC 0.18um process, from the layout level circuit to verification the single-phase adiabatic CAL SRAM low-power effect.
The static power consumption of single-phase SRAM circuit is the focus research in this paper. For CAL SRAM circuit leakage power consumption in sleep time, the first to application multi-threshold technology in power-gating switch circuit, design the power-gating multi-threshold switch to reduce the leakage power of CAL SRAM peripheral circuits, then designed to reduce the CAL SRAM cell circuit leakage power consumption in sleep time by applied drowsy cache technology. For CAL SRAM circuit when the runtime, we use dual-threshold technology and gate-length biasing technology to reduce this part leakage power consumption. The SRAM circuits that used leakage power reduction techniques all have been simulated by HSPICE, the simulation results show that the designed circuits have good effect to reduce the SRAM leakage power circuit.
Near threshold technique can be applied in the circuits that have low performance and frequency to substantial reduction the power consumption in these circuits. This paper applied near threshold technology in SRAM circuit, and to identify the maximum frequency and minimum energy delay product in different voltage.
引文
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