摘要
随着半导体工艺技术的不断发展,微处理器与主存速度差距的日益扩大,现代处理器都需要在片内设置一级或多级cache来缓解越来越严重的访存压力。此外,随着芯片容量的不断扩大,多核与多线程结构正成为当代处理器设计的主流。这些结构通过开发线程级并行性,极大地提高了处理器的计算吞吐率,但同时也对处理器存储子系统的访存吞吐能力提出了严重的挑战。处理器设计者需要在固定的芯片面积内权衡和折衷,或者增加内核数量或线程数量以获得更高的计算能力,或者增加片内Cache容量来提高处理器的访存能力,从而使这两种能力达到相互平衡,避免任何一种能力成为性能瓶颈。将压缩技术应用于片内cache数据的保存,能显著增加cache的有效容量,减少cache失效,缓解处理器计算能力与其访存压力之间的矛盾,使上述权衡向计算能力倾斜。但是,压缩cache技术也会给处理器的性能带来负面影响,因为,它在处理器的访存延迟中加入了数据解压缩的延迟开销,使cache的命中延迟增加。为此,本文以提升系统性能为目标,从简化压缩编码算法降低解压缩延迟,优化压缩cache层次结构,改善压缩cache替换策略等几个方面着手,对压缩cache的性能优化技术进行了深入研究,主要取得了以下一些研究成果:
1.对原本应用于L2 cache压缩的常见模式压缩(Frequent Pattern Compression,FPC)算法进行了简化,并分解了该算法的解压缩流程,提出并设计了一种基于简单常见模式压缩(Simple Frequent Pattern Compression,S-FPC)编码算法的解压缩流程,减少L2压缩cache行的解压缩延迟开销1个处理器周期,并且使该算法能被应用于L1数据cache的压缩。对简化后的压缩编码算法的压缩效果进行了模拟试验和评估,并详细描述了S-FPC压缩编码算法的硬件实现。
2.提出并设计了一种基于统一的简单常见模式压缩(S-FPC)编码的压缩cache层次结构UCCH(Unified Compressed Cache Hierarchy)。UCCH结构在L1数据cache和L2 cache以统一的压缩编码保存数据,能显著提高片内L1数据cache和L2 cache的有效容量。另外,在UCCH结构中,L1数据cache的压缩结合了部分cache行预取功能,可充分发挥预取技术显著降低cache失效率的优点,却不会招致通常的预取技术可能产生的cache污染与访存带宽需求增加的缺点,也不需要额外添加预取缓冲。UCCH结构的设计显著改善了压缩cache的性能。
3.提出了一种新颖的基于LRU修正的压缩cache替换策略MLRU-C(ModifiedLRU Replacement Policy for Compressed Cache),用于改善L2压缩cache的替换行为。MLRU-C替换策略利用压缩cache中额外的tag资源,构造了一种影子tag机制,该机制能对传统LRU替换策略经常出现的几种错误的cache替换行为进行鉴别,并将其记录到一个错误记录表MRT(Mistake Record Table)中,然后根据此记录表对LRU替换错误进行及时纠正。模拟实验表明,MLRU-C能有效地改善L2压缩cache的替换行为,减少L2压缩cache的失效率。
4.研究了压缩cache技术对多线程处理器性能的影响,并通过模拟实验验证了UCCH结构能够改善多线程处理器的性能。由于多线程处理器中有多个同时运行的线程共享整个片内cache层次结构,破坏了从L1数据cache到L2 cache的数据局部性,增大了cache失效率,并使L1-L2-主存之间的总线传输带宽压力显著增长,因此,虽然多线程处理器降低了对访存延迟的敏感性,但却显著增加了对cache层次结构的容量以及访问带宽的敏感性。由于UCCH结构能够显著增加L1数据cache和L2 cache的有效容量,同时由于在L1-L2-主存之间直接以压缩格式传输数据,能显著降低L1-L2-主存之间的总线传输带宽需求,因此UCCH结构能够改善SMT处理器的访存性能。
Since innovations in CMOS technology in recent years have led to performance gap between processor and memory widening, modern processors use one or more levels of on-chip caches to alleviate the ever-increasing pressure of memory accesses. In addition, as the chip density increasing, chip multiprocessors (MP) and multithreading (MT) are becoming mainstream architectures of current processor design. The both architectures can greatly improve processor performance and throughput by exploiting both thread-level and instruction-level parallelism, but the growing memory access demand in MP/MT environment challenge the throughput ability of their memory sub-system. The processor designer must determine the tradeoff between cores and caches in a fixed area budget so that neither cores nor caches is the only performance bottleneck. Compressed cache technology can change the tradeoff between cores and caches and allow a design where more on-chip area is allocated to processor cores since on-chip cache compression can increase the effective cache size without significantly increasing its area and avoid some misses. Unfortunately, cache compression also has a negative side effect, since compressed cache lines have to be decompressed before being used by processor. This means that storing compressed lines increases cache hit latency. So this paper researched on the compressed cache technology for performance optimization. The methods, such as optimizing compressed cache hierarchy, simplifying compressed algorithm and improving cache replacement policy etc. were proposed to improve performance of compressed cache.The main contributions of this paper are as follows:
1. With simplifying the Frequent Pattern Compression (FPC) algorithm, which used by L2 cache compression, and dividing the decompression process of compressed cache line into two stages, we proposed a novel decompression process of L2 compressed cache line based on Simple Frequent Pattern Compression (S-FPC) algorithm. The proposed scheme can decrease L2 decompressed latency 1 cycle and support compressing L1 data cache data. We evaluated the scheme by simulation experiments and described the hardware implementation of the compression scheme in detail.
2. We proposed a unified compressed cache hierarchy (UCCH) that uses a unified compression algorithm in both L1 D-cache and L2 cache, called Simple Frequent Pattern Compression (S-FPC). UCCH can increase the cache capacity of L1 D-cache and L2 cache without any sacrifice of the L1 cache access latency. The layout of compressed data in L1 data cache of UCCH enables partial cache line prefetching and does not introduce prefetch buffers or increase cache pollution and memory traffic. The experiment shows UCCH can distinctly improve the performance.
3. We proposed a novel modified LRU replacement policy for compressed cache (MLRU-C). MLRU-C replacement policy uses extra tags in compressed cache to construct a shadow tag struct, which be used to identify and record the mistake replacement in LRU policy. The mistake replacements in LRU policy recorded by shadow tag struct would be stored in Mistake Record Table (MRT). The MLRU-C would correct the mistake replacement decision according to the mistake replacement record in MRT. The experiment shows that MLRU-C can evidently decrease L2 compressed cache miss rate.
4. We proposed using compressed cache technology to improve multithreading processor performance. Because the data locality of L1 D-cache and L2 cache is hurted by sharing on-chip cache hierarchy between threads, MT technolgy distinctly increases the cache miss rate and memory traffic. The demands for cache capcity and data bus bandwidth between levels of caches increase apparently. Because our UCCH scheme can increase capacity of L1 D-cache and L2 cache and decrease miss rate of both L1 D-cache and L2 cache distinctly, it can alleviate the L1-L2-main memory bandwidth demand and improve the performance of MT processor.
引文
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