定点运算部件的算法结构研究与优化设计
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摘要
在IC设计领域,计算机微处理器是整个系统的核心,人们对其性能的要求越来越高,这些微处理器强有力的运算能力来源于其内部高性能的运算处理单元。加法在各类处理器中都是使用频率最高的操作,乘法的运算速度已成为衡量现代’高性能计算和数字信号处理性能的重要指标。加法器和乘法器的设计实现直接影响着微处理器的性能,这方面的研究依然是国内外微处理器设计的的重要课题。
本文分别对运算部件中最重要的整数加法器和乘法器进行了较为深入的研究,算法和电路逻辑结构的优化是本文的目标。针对加法器,对并行前缀结构进行了优化,将其与Ling进位和改进的选择进位模块相结合设计实现了一种新型的加法器。针对乘法器,采用了高性能的选择逻辑部分积产生电路,通过对部分积压缩阵列的研究和分析,设计实现了6：2和9：2压缩器,并利用9：2压缩器家族对整体拓扑结构进行了优化,实现了3种改进的并行乘法器和一种4周期串并结合的乘法器。
本文用Verilog HDL描述了所有设计思想,并完成了基于FPGA的电路综合与仿真验证。实验结果表明,同传统的实现结构相比,本文设计的新型加法器和改进的乘法器均具有更好的性能,达到了优化设计的目标。
In the field of IC design, microprocessor is the core part of a digital system due to which the requirement for its performance becomes higher and higher. The powerful operation ability comes from its internal arithmetic units, so it's of great value to design these units with high performance. Among most kinds of processors, adder is the most fundamental arithmetic component since addition is the most often used operation, while multiplier plays a key role in today's modern microprocessors and digital signal processors.
This paper focuses on the optimization of algorithm and logic circuit design of integer adder and multiplier. Based on the optimized parallel-prefix formulation, Ling carry and modified carry-select module, a new adder is presented. In the design of high-performance multiplier, a kind of select-logic partial product generating unit is employed. What's more, the design and realization of high order compressors 6:2 and 9:2 are completed by researching the partial product compressing array. Through optimizing the multiplier topology, this paper implemented three improved parallel multipliers and a four-cycle serial-parallel multiplier.
The whole design is described with Verilog HDL. The results of synthesis and simulation based on FPGA show that the new adder and the modified multipliers all have better performance compared with those using traditional methods.
本文分别对运算部件中最重要的整数加法器和乘法器进行了较为深入的研究,算法和电路逻辑结构的优化是本文的目标。针对加法器,对并行前缀结构进行了优化,将其与Ling进位和改进的选择进位模块相结合设计实现了一种新型的加法器。针对乘法器,采用了高性能的选择逻辑部分积产生电路,通过对部分积压缩阵列的研究和分析,设计实现了6：2和9：2压缩器,并利用9：2压缩器家族对整体拓扑结构进行了优化,实现了3种改进的并行乘法器和一种4周期串并结合的乘法器。
本文用Verilog HDL描述了所有设计思想,并完成了基于FPGA的电路综合与仿真验证。实验结果表明,同传统的实现结构相比,本文设计的新型加法器和改进的乘法器均具有更好的性能,达到了优化设计的目标。
In the field of IC design, microprocessor is the core part of a digital system due to which the requirement for its performance becomes higher and higher. The powerful operation ability comes from its internal arithmetic units, so it's of great value to design these units with high performance. Among most kinds of processors, adder is the most fundamental arithmetic component since addition is the most often used operation, while multiplier plays a key role in today's modern microprocessors and digital signal processors.
This paper focuses on the optimization of algorithm and logic circuit design of integer adder and multiplier. Based on the optimized parallel-prefix formulation, Ling carry and modified carry-select module, a new adder is presented. In the design of high-performance multiplier, a kind of select-logic partial product generating unit is employed. What's more, the design and realization of high order compressors 6:2 and 9:2 are completed by researching the partial product compressing array. Through optimizing the multiplier topology, this paper implemented three improved parallel multipliers and a four-cycle serial-parallel multiplier.
The whole design is described with Verilog HDL. The results of synthesis and simulation based on FPGA show that the new adder and the modified multipliers all have better performance compared with those using traditional methods.
引文
[1]B. Parhami. Computer Arithmetic Algorithms and Hardware Designs. USA: Oxford Univ. Press,2000.
[2]Lin Yu Shen, Radhakrishnan. Delay Efficient 32-bit Carry-Skip Adder. IEEE International Conference on Electronic Circuits and Systems.2006,12.506-509.
[3]R.P. Brent, H.T. Kung. A Regular Layout for Parallel Adders. IEEE Transactions on Computers.1982,31(3).260-264.
[4]H. Zhu, C. K. Cheng, R. Graham. On the construction of zero-deficiency parallel prefix circuits with minimum depth. ACM transactions on Design Automation of Electronic System.2006,11(2).387-409.
[5]S. Das, S. P. Khatri. A Novel Hybrid Parallel-Prefix Adder Architecture with Efficient Timing-Area Characteristic. IEEE Transactions on VLSI Systems.2008, 3,16(3).326-331.
[6]H. Ling. High.Speed Binary Adder. IBM Journal of Research and Development. 1981,25(3).156-166.
[7]R. W. Doran. Variants of an Improved Carry.Lookahead Adder. IEEE Transaction on Computers.1988,37.1110-1113.
[8]J. F. Li, J. D. Yu. A Design Methodology for Hybrid Carry-Lookahead/Carry-Select Adders with Reconfigurability. IEEE International Symposium on Circuits and Systems.2005,5.77-80.
[9]Dave. V, Oruklu. E, Saniie. J. Design and Synthesis of a Three Input Flagged Prefix Adder. IEEE International Symposium on Circuits and Systems.2007,3. 1081-1084.
[10]A. D. Booth. A Signed Binary Multiplication Technique. Quarterly Journal of Mechanics and Applied Mathematics.1951,6,4(2).236-240.
[11]L. McSorley. High Speed Arithmetic in Binary Computers. Proceedings of the IRE. 1961,1,49(1).67-91.
[12]K. Cho, J. Park, J. Hong.54 X 54-bit Radix-4 Multiplier based on Modified Booth Algorithm. GLS VLSI.2003.233-237.
[13]Hsin-Lei Lin, Chang, R. C. Design of a Novel Radix-4 Booth Multiplier. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems.2004,12.837-840.
[14]Shah.S, Al-Khalili.A.J. Comparison of 32-bit Multipliers for Various Performance Measures. The 12th Interantional Conference on Microelectronics.2000,10. 75-80.
[15]Jiangmin Gu, Chip-Hong Chang. Ultra Low Voltage, Low Power 4-2 Compressor for High Speed Multiplications. Proceedings of the 2003 International Sympposium on Circuits and Systems.2003,5,5.321-324.
[16]Howard. G. M, Mokrian. P. Power and Delay Analysis of 4:2 Compressor Cells. IEEE International Symposium on Circuits and Systems.2005,5,4.3559-3562.
[17]Kang. J. Y, Gaudiot. J. L. A Simple High-Speed Multiplier Design. IEEE Transactions on Computers.2006,10,55(10).1253-1258.
[18]J. P. Hu, L. Wang. A Low-Power Adiabatic Multiplier Based on Modified Booth Algorithm. IEEE International Symposium on Integrated Circuits.2007,9. 489-492.
[19]Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic数字集成电路设计透视.第2版.北京：清华大学出版社,2003.
[20]John F.Wakerly. Digital Design Principles&Practices影印版.高等教育出版社,2002.
[21]A. Tyagi. A reduced area scheme for carry.select adders. IEEE Transactions on Computer.1993,42.1163-1170.
[22]S. K. Mathew. Sub-500-ps 64-b ALUs in 0.18-um SOI/Bulk CMOS:Design and Scaling Trends. IEEE Journal of Solid-State Circuit.2001,11,36(11).1636-1646.
[23]Andrew. Bateman,陈建译.DSP算法、应用与设计.北京：机械工业出版社,2003.
[24]J. Liu, Y. Zhu. Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. IEEE Design Automation Conference.2007.609-615.
[25]K. Hwang. Computer Arithmetic Principles, Architecture and Design. New York: Wiley,1979.
[26]R. Hussin, N. Idris. Improved Booth Encoding for Reduce Area Multiplier. The IEEE International Conference on Semiconductor Electronics.2006,10.773-775.
[27]Vojin G, Oklobdzija. High.Speed VLSI Arithmetic Units:Adders and Multipliers. 1999,9.
[28]C. F. Law, S. S. Rofail, K. S. Yeo. A Low-Power 16 X 16-b Parallel Multiplier Utilizing Pass.Transistor Logic. IEEE Journal of Solid-State Circuits.1999,34. 1395-1399.
[29]蒋安平.专用32位浮点RISC的数据路径的研究,[博士学位论文].西安：陕西微电子技术研究所,1997.
[30]夏宇闻Veilog数字系统设计教程.北京：北京航空航天出版社,2003.
[31]Mark Balch完整的数字设计.影印版.北京：清华大学出版社,2003.145-173.
[32]王诚,吴继华Altera FPGA/CPLD设计.北京：人民邮电出版社,2005.
[33]王金明Verilog HDL程序设计教程.北京：人民邮电出版社,2004.3-17.
[2]Lin Yu Shen, Radhakrishnan. Delay Efficient 32-bit Carry-Skip Adder. IEEE International Conference on Electronic Circuits and Systems.2006,12.506-509.
[3]R.P. Brent, H.T. Kung. A Regular Layout for Parallel Adders. IEEE Transactions on Computers.1982,31(3).260-264.
[4]H. Zhu, C. K. Cheng, R. Graham. On the construction of zero-deficiency parallel prefix circuits with minimum depth. ACM transactions on Design Automation of Electronic System.2006,11(2).387-409.
[5]S. Das, S. P. Khatri. A Novel Hybrid Parallel-Prefix Adder Architecture with Efficient Timing-Area Characteristic. IEEE Transactions on VLSI Systems.2008, 3,16(3).326-331.
[6]H. Ling. High.Speed Binary Adder. IBM Journal of Research and Development. 1981,25(3).156-166.
[7]R. W. Doran. Variants of an Improved Carry.Lookahead Adder. IEEE Transaction on Computers.1988,37.1110-1113.
[8]J. F. Li, J. D. Yu. A Design Methodology for Hybrid Carry-Lookahead/Carry-Select Adders with Reconfigurability. IEEE International Symposium on Circuits and Systems.2005,5.77-80.
[9]Dave. V, Oruklu. E, Saniie. J. Design and Synthesis of a Three Input Flagged Prefix Adder. IEEE International Symposium on Circuits and Systems.2007,3. 1081-1084.
[10]A. D. Booth. A Signed Binary Multiplication Technique. Quarterly Journal of Mechanics and Applied Mathematics.1951,6,4(2).236-240.
[11]L. McSorley. High Speed Arithmetic in Binary Computers. Proceedings of the IRE. 1961,1,49(1).67-91.
[12]K. Cho, J. Park, J. Hong.54 X 54-bit Radix-4 Multiplier based on Modified Booth Algorithm. GLS VLSI.2003.233-237.
[13]Hsin-Lei Lin, Chang, R. C. Design of a Novel Radix-4 Booth Multiplier. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems.2004,12.837-840.
[14]Shah.S, Al-Khalili.A.J. Comparison of 32-bit Multipliers for Various Performance Measures. The 12th Interantional Conference on Microelectronics.2000,10. 75-80.
[15]Jiangmin Gu, Chip-Hong Chang. Ultra Low Voltage, Low Power 4-2 Compressor for High Speed Multiplications. Proceedings of the 2003 International Sympposium on Circuits and Systems.2003,5,5.321-324.
[16]Howard. G. M, Mokrian. P. Power and Delay Analysis of 4:2 Compressor Cells. IEEE International Symposium on Circuits and Systems.2005,5,4.3559-3562.
[17]Kang. J. Y, Gaudiot. J. L. A Simple High-Speed Multiplier Design. IEEE Transactions on Computers.2006,10,55(10).1253-1258.
[18]J. P. Hu, L. Wang. A Low-Power Adiabatic Multiplier Based on Modified Booth Algorithm. IEEE International Symposium on Integrated Circuits.2007,9. 489-492.
[19]Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic数字集成电路设计透视.第2版.北京：清华大学出版社,2003.
[20]John F.Wakerly. Digital Design Principles&Practices影印版.高等教育出版社,2002.
[21]A. Tyagi. A reduced area scheme for carry.select adders. IEEE Transactions on Computer.1993,42.1163-1170.
[22]S. K. Mathew. Sub-500-ps 64-b ALUs in 0.18-um SOI/Bulk CMOS:Design and Scaling Trends. IEEE Journal of Solid-State Circuit.2001,11,36(11).1636-1646.
[23]Andrew. Bateman,陈建译.DSP算法、应用与设计.北京：机械工业出版社,2003.
[24]J. Liu, Y. Zhu. Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. IEEE Design Automation Conference.2007.609-615.
[25]K. Hwang. Computer Arithmetic Principles, Architecture and Design. New York: Wiley,1979.
[26]R. Hussin, N. Idris. Improved Booth Encoding for Reduce Area Multiplier. The IEEE International Conference on Semiconductor Electronics.2006,10.773-775.
[27]Vojin G, Oklobdzija. High.Speed VLSI Arithmetic Units:Adders and Multipliers. 1999,9.
[28]C. F. Law, S. S. Rofail, K. S. Yeo. A Low-Power 16 X 16-b Parallel Multiplier Utilizing Pass.Transistor Logic. IEEE Journal of Solid-State Circuits.1999,34. 1395-1399.
[29]蒋安平.专用32位浮点RISC的数据路径的研究,[博士学位论文].西安：陕西微电子技术研究所,1997.
[30]夏宇闻Veilog数字系统设计教程.北京：北京航空航天出版社,2003.
[31]Mark Balch完整的数字设计.影印版.北京：清华大学出版社,2003.145-173.
[32]王诚,吴继华Altera FPGA/CPLD设计.北京：人民邮电出版社,2005.
[33]王金明Verilog HDL程序设计教程.北京：人民邮电出版社,2004.3-17.