时间交织模数转换器中的模拟电路关键技术研究及其集成应用
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摘要
随着器件尺寸的缩小,数字电路获得了迅猛的发展。数字信号处理技术广泛应用于通信、计算机、仪表控制等领域。这对于模拟与数字世界的接口电路——模数转换器(ADC)的性能提出了极高的要求。然而,在当前的工艺条件下,各种结构的ADC经过长期的研究都日趋成熟,速度与精度的提升空间已经越来越小。
在这种情况下,时间交织结构ADC体现出了它的发展潜力。时间交织ADC将多通道子ADC并行工作,可以大大提高整体ADC的转换速度。但是,通道间的失调失配、增益失配以及采样时刻偏差等不匹配因素限制了它的实际性能,因此需要对其进行校准。除了子通道ADC与校准模块,使子ADC实现时间交织结构的模拟电路也是时间交织ADC不可或缺的组成部分。这也是本文的主要研究内容。
本文首先讨论了影响时间交织ADC性能的关键模拟电路技术,比如时钟信号的管理,参考电压源等。在此基础上,为一款14比特200兆采样/秒的双通道时间交织ADC设计了其时间交织模拟集成电路部分。
本文的设计主要集中于两个部分：时钟网络以及直流电平供给网络。时钟网络包括低抖动时钟产生电路和低偏移二分频器,用以产生低误差的采样时钟。直流电平供给网络包括：1)一个带隙基准电压源,用来产生低温漂、稳定性好的片内基准源；2)基准电压源电阻分压驱动网络,用以驱动各个直流电平；3)参考电压源产生电路,为子通道ADC提供精准的片上参考电压。
为了验证本设计的功能,本文以一款14比特100兆采样/秒的流水线ADC为子ADC,并与一个数字后台校准模块共同构成了一个双通道时间交织ADC。该ADC采用SMIC的0.18-μm CMOS工艺实现。芯片核心面积为22.5 mm2,在1.8伏电源电压下核心功耗为490 mW(不包括数字输出驱动缓冲器)。测试结果显示,经数字后台校准,该ADC的微分非线性度(DNL)和积分非线性度(INL)分别为+0.20/-0.19 LSB和+1.3/-1.4 LSB,达到了14比特线性度。在200兆采样率下,该ADC对15.3兆赫兹的输入信号,可以达到88.9 dBc的无杂散动态范围(SFDR)和69.5 dB的信号噪声失真比(SNDR)
Scaling of CMOS technology bring clear advantage of digital circuitry and Digital Signal Processing(DSP) is widely used in communication, computer, instrument and other fields. As the interface of analog and digital world, Analog-to-Digital Conver(ADC)'s requirements is also increased by this trend. However, within present technology, ADC's performance is approaching limitations after years of research.
Time interleaving of ADCs is an attractive way to increase the overall conversion rate in a given technology while providing high resolution. With M ADC channels operating in parallel, the overall sampling rate increases by the factor M over that of a single channel. However, mismatches among the channel ADCs, such as gain mismatches, offset mismatches, sample-time errors, can significantly degrade the SNDR and SFDR of the system. As a result, calibration block is needed in time-interleaved ADCs. Besides, the analog circuit also plays an improtant role in the performance of time-interleaved ADC, such as clock management and reference voltage generator. This paper is focused on the research of critical analog circuits in time-interleaved ADCs and proposed analog part for a two-channle 14-bit 200-MS/s time-interleaved ADC.
The circuits designed in this paper can be divided into two parts:clock manegement and power supply. The clock citcuit includes a low-jitter clock driver, a low-skew clock divider; the power supply is consists of three parts:a bandgap voltage reference, high performance buffers and a differential reference used in high-speed high-resolution pipelined ADC.
Based on the proposed analog circuits and a calibration block, a two-channel 14-bit 200-MS/s time-interleaved ADC is achieved. The proposed ADC is fabricated in SMIC 0.18-μm CMOS Mixed-Signal process occupying 22.5 mm2 die area and consuming 490 mW (excluding output driver) at 1.8V power supply. Measurements shows that, after calibration, the ADC achieves 14-bit linearity with +0.20/-0.19 LSB DNL and +1.3/-1.4 LSB INL. At 200 MS/s, the ADC acheives 88.9 dBc SFDR and 69.5 dB SNDR for an input signal of 15.3 MHz.
在这种情况下,时间交织结构ADC体现出了它的发展潜力。时间交织ADC将多通道子ADC并行工作,可以大大提高整体ADC的转换速度。但是,通道间的失调失配、增益失配以及采样时刻偏差等不匹配因素限制了它的实际性能,因此需要对其进行校准。除了子通道ADC与校准模块,使子ADC实现时间交织结构的模拟电路也是时间交织ADC不可或缺的组成部分。这也是本文的主要研究内容。
本文首先讨论了影响时间交织ADC性能的关键模拟电路技术,比如时钟信号的管理,参考电压源等。在此基础上,为一款14比特200兆采样/秒的双通道时间交织ADC设计了其时间交织模拟集成电路部分。
本文的设计主要集中于两个部分：时钟网络以及直流电平供给网络。时钟网络包括低抖动时钟产生电路和低偏移二分频器,用以产生低误差的采样时钟。直流电平供给网络包括：1)一个带隙基准电压源,用来产生低温漂、稳定性好的片内基准源；2)基准电压源电阻分压驱动网络,用以驱动各个直流电平；3)参考电压源产生电路,为子通道ADC提供精准的片上参考电压。
为了验证本设计的功能,本文以一款14比特100兆采样/秒的流水线ADC为子ADC,并与一个数字后台校准模块共同构成了一个双通道时间交织ADC。该ADC采用SMIC的0.18-μm CMOS工艺实现。芯片核心面积为22.5 mm2,在1.8伏电源电压下核心功耗为490 mW(不包括数字输出驱动缓冲器)。测试结果显示,经数字后台校准,该ADC的微分非线性度(DNL)和积分非线性度(INL)分别为+0.20/-0.19 LSB和+1.3/-1.4 LSB,达到了14比特线性度。在200兆采样率下,该ADC对15.3兆赫兹的输入信号,可以达到88.9 dBc的无杂散动态范围(SFDR)和69.5 dB的信号噪声失真比(SNDR)
Scaling of CMOS technology bring clear advantage of digital circuitry and Digital Signal Processing(DSP) is widely used in communication, computer, instrument and other fields. As the interface of analog and digital world, Analog-to-Digital Conver(ADC)'s requirements is also increased by this trend. However, within present technology, ADC's performance is approaching limitations after years of research.
Time interleaving of ADCs is an attractive way to increase the overall conversion rate in a given technology while providing high resolution. With M ADC channels operating in parallel, the overall sampling rate increases by the factor M over that of a single channel. However, mismatches among the channel ADCs, such as gain mismatches, offset mismatches, sample-time errors, can significantly degrade the SNDR and SFDR of the system. As a result, calibration block is needed in time-interleaved ADCs. Besides, the analog circuit also plays an improtant role in the performance of time-interleaved ADC, such as clock management and reference voltage generator. This paper is focused on the research of critical analog circuits in time-interleaved ADCs and proposed analog part for a two-channle 14-bit 200-MS/s time-interleaved ADC.
The circuits designed in this paper can be divided into two parts:clock manegement and power supply. The clock citcuit includes a low-jitter clock driver, a low-skew clock divider; the power supply is consists of three parts:a bandgap voltage reference, high performance buffers and a differential reference used in high-speed high-resolution pipelined ADC.
Based on the proposed analog circuits and a calibration block, a two-channel 14-bit 200-MS/s time-interleaved ADC is achieved. The proposed ADC is fabricated in SMIC 0.18-μm CMOS Mixed-Signal process occupying 22.5 mm2 die area and consuming 490 mW (excluding output driver) at 1.8V power supply. Measurements shows that, after calibration, the ADC achieves 14-bit linearity with +0.20/-0.19 LSB DNL and +1.3/-1.4 LSB INL. At 200 MS/s, the ADC acheives 88.9 dBc SFDR and 69.5 dB SNDR for an input signal of 15.3 MHz.
引文
[1]B. Brannon, B. Schofield. TD-SCDMA多载波系统可行性研究[EB/OL].http://www.analog.com/static/imported-files/zh/application_notes/AN-808_cn.pdf.
[2]罗磊,14比特100兆采样/秒流水线型模数转换器[D].上海：复旦大学.2009.
[3]W. C. Black, Jr. and D. A. Hodges, Time interleaved converter arrays[J]. IEEE Journal of Solid-State Circuits,1980,15:1022-1029.
[4]Y.-T. Wang, B. Razavi, An 8bit 150MHz CMOS A/D Converter[C]. Digest Technical Papers, Custom Integrated Circuits Conference, USA,1999:117-120.
[5]K. C. Dyer, D. Fu, S. H. Lewis, et al. An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters[J]. IEEE Journal of Solid-State Circuits, 1998,33:1912-1919.
[6]C.-C. Hsu, F.-C. Huang, C.-Y. Shin, et al. An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration[C]. Digest Technical Papers,54th International Solid-State Circuits Conference, San Francisco, USA,2007:464-465.
[7]S. M. Jamal, D. Fu, M. P. Singh, et al. Calibration of sample-time error in two-channel time-interleaved analog-to-digital converter[J]. IEEE Transaction on Circuits and Systems Ⅰ, Regular Papers,2004,51(1):130-139.
[8]H.Jin, E. K. F. Lee. A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC's[J]. IEEE Transaction on Circuits and Systems II, Express Briefs,2000,47:603-613.
[9]J. Elbornsson, F. Gustafsson, and J.-E. Eklund, Blind Adaptive Equalization of Mismatch Errors in a Time-Interleaved A/D Converter System[J]. IEEE Transaction on Circuits and Systems Ⅰ, Regular Papers,2004,51:151-158.
[10]陈廷乾.高速、高精度流水线模数转换器设计研究[D].上海：复旦大学.2008.
[11]施宇峰.10比特1.8伏100兆赫兹流水线模数转换器[D].上海：复旦大学.2005.
[12]Mok W, Mak P.Martins R, et al. Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC [EB/OL].:http://ieeexplore.ieee.org/ stamp/stamp.jsp?tp=&arnumber=1353883.
[13]Shinagawa M, Akazawa Y, Wakimoto T. Jitter Analysis of High-Speed Sampling Systems[J]. IEEE Journal of Solid-State Circuits,1990,25:220-224.
[14]Zanchi A, Tsay F. A 16-bit 65-MS/s 3.3-V Pipeline ADC Core in SiGe BiCMOS With 78-dB SNR and 180-fs Jitter[J]. IEEE Journal of Solid-State Circuits,2005,40: 1225-1237.
[15]程龙,罗磊,任俊彦.宽带ADC低抖动时钟驱动电路的分析和设计[J].复旦学报,2009,48(4)：499-505.
[16]Ohns D, Martin K. Analog Integrated Circuit Design [M]. New York:John Wiley & Sons,1997.
[17]李联.MOS运算放大器——原理、设计与应用[M].上海：复旦大学出版社,1988.
[18]Singer L, Ho S, Timko M, et al. A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz [EB/OL].:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=839681.
[19]Boni A. Op-amps and startup circuits for CMOS bandgap references with near 1-V supply [J]. IEEE Journal of Solid-State Circuits,2002,37(10):1339-1343.
[20]Buck A, McDonald C, Lewis S, et al. A CMOS bandgap reference without resistors [J]. IEEE Journal of Solid-State Circuits,2002,37(1):81-83.
[21]Zanchi A, Tsay F. A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter [J]. IEEE Journal of Solid-State Circuits,2005,40(6): 1225-1237.
[22]Kenney J, Rangan G, Ramamurthy K, et al. An enhanced slew rate source follower[J]. IEEE Journal of Solid-State Circuits,1995,30(2):144-146.
[23]T. Brooks, et al. A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR[J]. IEEE Journal of Solid-State Circuits,1997,32(12): 1896-1906.
[24]L.Sumanen. Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications[D]. Finland:Helsinki University of Technology,2002.
[25]Li JP. Accuracy Enhancement Techniques in Low-Voltage High-Speed Pipelined ADC Design[D]. Oregon State University,2004.
[26]YM Lin, B Kim, PR Gray. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS[J]. IEEE Journal of Solid-State Circuits,1991,26:628.
[27]BS Song, MF Tompsett, KR Lakshmikumar. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter[J]. IEEE Journal of Solid-State Circuits,1988, 23(6):1324-1333.
[28]PC Yu, HS Lee. A 2.5-V 12-b 5-Msample/s pipelined CMOS ADC[J]. IEEE Journal of Solid-State Circuits,1996,31(12):854-1861.
[29]OE. Erdogan, PJ Hurst, SH Lewis. A 12-b Digital-background-calibrated algorithmid ADC with -90-dB THD[J]. IEEE Journal of Solid-State Circuits,1999,34:1812.
[30]HC Liu, ZM Lee, JT Wu. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration[J]. IEEE Journal of Solid-State Circuits,2005, 40:1047.
[31]J Li, UK Moon. Background calibration techniques for multistage pipelined ADCs with digital redundancy[J]. IEEE Trans. Circuits Syst.Ⅱ,2003,50:531.
[32]叶凡.多通道时间交织模数转换器的校正与集成电路实现方法研究[D].上海：复旦大学.2010.
[33]R. G. Lyons数字信号处理(第二版)[M],北京：机械工业出版社,2006：292.
[34]S. Haykin自适应滤波器原理(第四版)[M],北京：电子工业出版社,2003：183.
[35]A. V. Oppenheim, R. W. Schafer, J. R. Buck离散时间信号处理(第二版),西安：西安交通大学出版社,2001：139.
[36]C.Saint, J. Saint集成电路版图设计——基础版图技术[M],北京：清华大学出版社,2006：120.
[37]Analog-Digital Conversion,Chapter 5:Testing Data Converters, Analog Devices, [EB/OL].: http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook .html.
[38]P Bogner, et al. A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13um CMOS[C]. IEEE ISSCC 2006.
[39]BG Lee, et al. A 14b 100Ms/s Pipelined ADC with a Merged Active S/H and First MDAC[C]. IEEE ISSCC 2008.
[40]Limotyrakis S, Kulchycki S.D, SU D, et al. A 150 MS/s 8b 71 mW time-interleaved ADC in 0.18 μm CMOS[C]. Digest Technical Papers,51th International Solid-State Circuits Conference, San Francisco, USA,2004:258-259.
[41]Z.-M. Lee, C.-Y. Wang and J.-T. Wu. A CMOS 15-bit 125-MS/s Time- Interleaved ADC with Digital Background Calibration[J]. IEEE Journal of Solid-State Circuits,2007, 42:2149-2160.
[42]S.-W. Sin, Seng-Pan U, R.P. Martins.1.2-V,10-bit,60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18μm CMOS with minimised supply headroom[J]. IET Circuits Devices Syst,2010,4(1):1-13.
[2]罗磊,14比特100兆采样/秒流水线型模数转换器[D].上海：复旦大学.2009.
[3]W. C. Black, Jr. and D. A. Hodges, Time interleaved converter arrays[J]. IEEE Journal of Solid-State Circuits,1980,15:1022-1029.
[4]Y.-T. Wang, B. Razavi, An 8bit 150MHz CMOS A/D Converter[C]. Digest Technical Papers, Custom Integrated Circuits Conference, USA,1999:117-120.
[5]K. C. Dyer, D. Fu, S. H. Lewis, et al. An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters[J]. IEEE Journal of Solid-State Circuits, 1998,33:1912-1919.
[6]C.-C. Hsu, F.-C. Huang, C.-Y. Shin, et al. An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration[C]. Digest Technical Papers,54th International Solid-State Circuits Conference, San Francisco, USA,2007:464-465.
[7]S. M. Jamal, D. Fu, M. P. Singh, et al. Calibration of sample-time error in two-channel time-interleaved analog-to-digital converter[J]. IEEE Transaction on Circuits and Systems Ⅰ, Regular Papers,2004,51(1):130-139.
[8]H.Jin, E. K. F. Lee. A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC's[J]. IEEE Transaction on Circuits and Systems II, Express Briefs,2000,47:603-613.
[9]J. Elbornsson, F. Gustafsson, and J.-E. Eklund, Blind Adaptive Equalization of Mismatch Errors in a Time-Interleaved A/D Converter System[J]. IEEE Transaction on Circuits and Systems Ⅰ, Regular Papers,2004,51:151-158.
[10]陈廷乾.高速、高精度流水线模数转换器设计研究[D].上海：复旦大学.2008.
[11]施宇峰.10比特1.8伏100兆赫兹流水线模数转换器[D].上海：复旦大学.2005.
[12]Mok W, Mak P.Martins R, et al. Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC [EB/OL].:http://ieeexplore.ieee.org/ stamp/stamp.jsp?tp=&arnumber=1353883.
[13]Shinagawa M, Akazawa Y, Wakimoto T. Jitter Analysis of High-Speed Sampling Systems[J]. IEEE Journal of Solid-State Circuits,1990,25:220-224.
[14]Zanchi A, Tsay F. A 16-bit 65-MS/s 3.3-V Pipeline ADC Core in SiGe BiCMOS With 78-dB SNR and 180-fs Jitter[J]. IEEE Journal of Solid-State Circuits,2005,40: 1225-1237.
[15]程龙,罗磊,任俊彦.宽带ADC低抖动时钟驱动电路的分析和设计[J].复旦学报,2009,48(4)：499-505.
[16]Ohns D, Martin K. Analog Integrated Circuit Design [M]. New York:John Wiley & Sons,1997.
[17]李联.MOS运算放大器——原理、设计与应用[M].上海：复旦大学出版社,1988.
[18]Singer L, Ho S, Timko M, et al. A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz [EB/OL].:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=839681.
[19]Boni A. Op-amps and startup circuits for CMOS bandgap references with near 1-V supply [J]. IEEE Journal of Solid-State Circuits,2002,37(10):1339-1343.
[20]Buck A, McDonald C, Lewis S, et al. A CMOS bandgap reference without resistors [J]. IEEE Journal of Solid-State Circuits,2002,37(1):81-83.
[21]Zanchi A, Tsay F. A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter [J]. IEEE Journal of Solid-State Circuits,2005,40(6): 1225-1237.
[22]Kenney J, Rangan G, Ramamurthy K, et al. An enhanced slew rate source follower[J]. IEEE Journal of Solid-State Circuits,1995,30(2):144-146.
[23]T. Brooks, et al. A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR[J]. IEEE Journal of Solid-State Circuits,1997,32(12): 1896-1906.
[24]L.Sumanen. Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications[D]. Finland:Helsinki University of Technology,2002.
[25]Li JP. Accuracy Enhancement Techniques in Low-Voltage High-Speed Pipelined ADC Design[D]. Oregon State University,2004.
[26]YM Lin, B Kim, PR Gray. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS[J]. IEEE Journal of Solid-State Circuits,1991,26:628.
[27]BS Song, MF Tompsett, KR Lakshmikumar. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter[J]. IEEE Journal of Solid-State Circuits,1988, 23(6):1324-1333.
[28]PC Yu, HS Lee. A 2.5-V 12-b 5-Msample/s pipelined CMOS ADC[J]. IEEE Journal of Solid-State Circuits,1996,31(12):854-1861.
[29]OE. Erdogan, PJ Hurst, SH Lewis. A 12-b Digital-background-calibrated algorithmid ADC with -90-dB THD[J]. IEEE Journal of Solid-State Circuits,1999,34:1812.
[30]HC Liu, ZM Lee, JT Wu. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration[J]. IEEE Journal of Solid-State Circuits,2005, 40:1047.
[31]J Li, UK Moon. Background calibration techniques for multistage pipelined ADCs with digital redundancy[J]. IEEE Trans. Circuits Syst.Ⅱ,2003,50:531.
[32]叶凡.多通道时间交织模数转换器的校正与集成电路实现方法研究[D].上海：复旦大学.2010.
[33]R. G. Lyons数字信号处理(第二版)[M],北京：机械工业出版社,2006：292.
[34]S. Haykin自适应滤波器原理(第四版)[M],北京：电子工业出版社,2003：183.
[35]A. V. Oppenheim, R. W. Schafer, J. R. Buck离散时间信号处理(第二版),西安：西安交通大学出版社,2001：139.
[36]C.Saint, J. Saint集成电路版图设计——基础版图技术[M],北京：清华大学出版社,2006：120.
[37]Analog-Digital Conversion,Chapter 5:Testing Data Converters, Analog Devices, [EB/OL].: http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook .html.
[38]P Bogner, et al. A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13um CMOS[C]. IEEE ISSCC 2006.
[39]BG Lee, et al. A 14b 100Ms/s Pipelined ADC with a Merged Active S/H and First MDAC[C]. IEEE ISSCC 2008.
[40]Limotyrakis S, Kulchycki S.D, SU D, et al. A 150 MS/s 8b 71 mW time-interleaved ADC in 0.18 μm CMOS[C]. Digest Technical Papers,51th International Solid-State Circuits Conference, San Francisco, USA,2004:258-259.
[41]Z.-M. Lee, C.-Y. Wang and J.-T. Wu. A CMOS 15-bit 125-MS/s Time- Interleaved ADC with Digital Background Calibration[J]. IEEE Journal of Solid-State Circuits,2007, 42:2149-2160.
[42]S.-W. Sin, Seng-Pan U, R.P. Martins.1.2-V,10-bit,60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18μm CMOS with minimised supply headroom[J]. IET Circuits Devices Syst,2010,4(1):1-13.