适用于无线传感网的射频收发机的关键技术
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摘要
随着无线传感网技术的飞速发展，对节点单芯片片上系统的需求越来越迫切，而射频电路的设计是节点芯片设计的瓶颈。本论文研究了适用于无线传感网的射频收发机中的一些关键技术，完成了以下工作，并全部进行了流片验证：
针对适用于无线传感网的收发机的低开销、灵活、低功耗和易开发等要求，设计了系统方案并进行指标规划。
针对无线传感网收发机低开销、灵活和镜像抑制的要求，提出一种低噪声、大动态范围、带镜像抑制的射频接收前端方案，并给出了有源RC复数滤波器的设计流程，提出一种数控电容阵列的实现方法用于有源RC电路的时间常数调谐。同时，提出一种低开销的本振信号产生方法，通过一个1.72GHz～1.74GHz的锁相环和一个四分频器的组合，来实现430MHz～435MHz的频率输出，为低中频的接收机提供两路正交的本振信号；为四分频器建立杂散模型，并在此基础上设计了一个低杂散、低噪声、低功耗的四分频器，以改善接收机的邻信道选择性。
针对无线传感网收发机低功耗、低开销的要求，提出了一种10.6mW功耗、18～25μs建立时间的锁相环频率综合器。采用键合线作为压控振荡器的电感，降低了功耗和芯片面积，同时也降低了相位噪声，这有助于改善接收机的邻信道选择性。提出一种快速自动频率校正机制，来校正键合线电感造成的谐振频率偏差，并提出基于电阻的静电释放保护电路，来增大频率校正范围。还提出了一种动态环路带宽机制，以满足时分复用的半双工无线传感网系统的需求，并建立模型来预测锁相环在不同带宽下噪声的分布。此外，为支持高斯频移键控的频率综合器的数字部分提供了一套可测试性设计，并为预分频器提出一种多级功耗缩放技术进一步降低了频率综合器的功耗。
针对无线传感网收发机的低功耗和灵活的要求，提出了一种5dB最小输入信噪比、5.9mW功耗、55.4dB动态范围的全模拟中频电路方案。其中限幅放大器和信号幅度指示器采用折叠结构的放大器单元与电流减法器结构的整流器单元的组合，能有效的抑制工艺偏差的影响。同时，考虑到整流器的非线性和静态电流，我们提出一种精确的信号幅度指示器传输函数的逼近模型，并提供了基于这种逼近模型的信号幅度指示器设计流程。此外，提出一套基于有源RC结构的高斯频移键控解调方案，具有低功耗、大动态范围的优点。
With the rapid development of the technologies in the field of wireless sensor net-works, the requirements for system on chip are becoming more and more urgent, and theradio-frequency part is the bottleneck to design a node chip. This dissertation investi-gates the key technologies of radio-frequency transceivers for wireless sensor networks,and the following works are completed and taped out:
To meet the requirements on low cost, flexibility, low power, and easy developmentof transceivers for wireless sensor networks, we design a system architecture, and makean assignment of the specifications.
To meet the requirements on low cost, flexibility, and image rejection of transceiversfor wireless sensor networks, we propose a low-noise large-dynamic-range radio-frequency receiving front end with image rejection, and give the design flow of active-RCcomplex filters. Meanwhile, we propose an implementation method of digital-controlledcapacitor arrays that can be used for the tuning of active-RC circuits. In addition, we pro-pose a method for low-cost generation of local oscillation, which is composed of a1.72GHz～1.74GHz phase-locked loop and a÷4divider. Then, the desired430MHz～435MHz output signals can be obtained, and the low-intermediate-frequency receiver can besupplied with both in-phase and quadrature-phase local oscillating signals. After that webuild a model for the÷4divider, and design a low-spur, low-noise and low-power÷4divider based on the model, and then the adjacent channel selectivity of the receiver canbe improved.
To meet the requirements on low cost and low power of transceivers for wirelesssensor networks, we propose a10.6mW phase-locked loop frequency synthesizer with18～25μs settling time. Bond wires are adopted as the inductors of the voltage-controlledoscillator, and then the power consumption, the die area and the phase noise are all de-creased. Therefore, the adjacent channel selectivity can be improved. A scheme of fastautomatic frequency calibration is proposed to calibrate the frequency deviations inducedby the bond-wire inductors, and a resistor based electro-static discharge protection circuitis proposed to enlarge the calibration range. Additionally, a dynamic-bandwidth schemeis also proposed to meet the requirements of time-division half-duplex wireless sensor networks, and an analytical model is built to forecast the noise distribution under difer-ent bandwidths of a phase-locked loop. Furthermore, we build a design-for-testabilityscheme for the frequency synthesizer with gauss frequency shift keying, and propose amulti-stage power-scaling technology for the prescaler to further reduce the power con-sumption of the frequency synthesizer.
To meet the requirements on low power and flexibility of transceivers for wirelesssensor networks, we propose an all-analog intermediate-frequency circuit with5dB min-imum input signal-to-noise ratio,5.9mW power, and a55.4dB dynamic range. The lim-iting amplifier and received signal strength indicator is composed of folded amplifiers,folded subtractors, and current subtractor based rectifiers, and then the process deviationscan be depressed efectively. Taking into account the nonlinearity and static current ofthe rectifiers, we propose an accurate approximation model of the received signal strengthindicator’s transfer function, and provide a design flow of received signal strength indica-tors assisted by the proposed model. In addition, we proposed an active-RC demodulationscheme for gauss frequency shift keying, and the scheme has the advantages of low powerand a large dynamic range.
针对适用于无线传感网的收发机的低开销、灵活、低功耗和易开发等要求，设计了系统方案并进行指标规划。
针对无线传感网收发机低开销、灵活和镜像抑制的要求，提出一种低噪声、大动态范围、带镜像抑制的射频接收前端方案，并给出了有源RC复数滤波器的设计流程，提出一种数控电容阵列的实现方法用于有源RC电路的时间常数调谐。同时，提出一种低开销的本振信号产生方法，通过一个1.72GHz～1.74GHz的锁相环和一个四分频器的组合，来实现430MHz～435MHz的频率输出，为低中频的接收机提供两路正交的本振信号；为四分频器建立杂散模型，并在此基础上设计了一个低杂散、低噪声、低功耗的四分频器，以改善接收机的邻信道选择性。
针对无线传感网收发机低功耗、低开销的要求，提出了一种10.6mW功耗、18～25μs建立时间的锁相环频率综合器。采用键合线作为压控振荡器的电感，降低了功耗和芯片面积，同时也降低了相位噪声，这有助于改善接收机的邻信道选择性。提出一种快速自动频率校正机制，来校正键合线电感造成的谐振频率偏差，并提出基于电阻的静电释放保护电路，来增大频率校正范围。还提出了一种动态环路带宽机制，以满足时分复用的半双工无线传感网系统的需求，并建立模型来预测锁相环在不同带宽下噪声的分布。此外，为支持高斯频移键控的频率综合器的数字部分提供了一套可测试性设计，并为预分频器提出一种多级功耗缩放技术进一步降低了频率综合器的功耗。
针对无线传感网收发机的低功耗和灵活的要求，提出了一种5dB最小输入信噪比、5.9mW功耗、55.4dB动态范围的全模拟中频电路方案。其中限幅放大器和信号幅度指示器采用折叠结构的放大器单元与电流减法器结构的整流器单元的组合，能有效的抑制工艺偏差的影响。同时，考虑到整流器的非线性和静态电流，我们提出一种精确的信号幅度指示器传输函数的逼近模型，并提供了基于这种逼近模型的信号幅度指示器设计流程。此外，提出一套基于有源RC结构的高斯频移键控解调方案，具有低功耗、大动态范围的优点。
With the rapid development of the technologies in the field of wireless sensor net-works, the requirements for system on chip are becoming more and more urgent, and theradio-frequency part is the bottleneck to design a node chip. This dissertation investi-gates the key technologies of radio-frequency transceivers for wireless sensor networks,and the following works are completed and taped out:
To meet the requirements on low cost, flexibility, low power, and easy developmentof transceivers for wireless sensor networks, we design a system architecture, and makean assignment of the specifications.
To meet the requirements on low cost, flexibility, and image rejection of transceiversfor wireless sensor networks, we propose a low-noise large-dynamic-range radio-frequency receiving front end with image rejection, and give the design flow of active-RCcomplex filters. Meanwhile, we propose an implementation method of digital-controlledcapacitor arrays that can be used for the tuning of active-RC circuits. In addition, we pro-pose a method for low-cost generation of local oscillation, which is composed of a1.72GHz～1.74GHz phase-locked loop and a÷4divider. Then, the desired430MHz～435MHz output signals can be obtained, and the low-intermediate-frequency receiver can besupplied with both in-phase and quadrature-phase local oscillating signals. After that webuild a model for the÷4divider, and design a low-spur, low-noise and low-power÷4divider based on the model, and then the adjacent channel selectivity of the receiver canbe improved.
To meet the requirements on low cost and low power of transceivers for wirelesssensor networks, we propose a10.6mW phase-locked loop frequency synthesizer with18～25μs settling time. Bond wires are adopted as the inductors of the voltage-controlledoscillator, and then the power consumption, the die area and the phase noise are all de-creased. Therefore, the adjacent channel selectivity can be improved. A scheme of fastautomatic frequency calibration is proposed to calibrate the frequency deviations inducedby the bond-wire inductors, and a resistor based electro-static discharge protection circuitis proposed to enlarge the calibration range. Additionally, a dynamic-bandwidth schemeis also proposed to meet the requirements of time-division half-duplex wireless sensor networks, and an analytical model is built to forecast the noise distribution under difer-ent bandwidths of a phase-locked loop. Furthermore, we build a design-for-testabilityscheme for the frequency synthesizer with gauss frequency shift keying, and propose amulti-stage power-scaling technology for the prescaler to further reduce the power con-sumption of the frequency synthesizer.
To meet the requirements on low power and flexibility of transceivers for wirelesssensor networks, we propose an all-analog intermediate-frequency circuit with5dB min-imum input signal-to-noise ratio,5.9mW power, and a55.4dB dynamic range. The lim-iting amplifier and received signal strength indicator is composed of folded amplifiers,folded subtractors, and current subtractor based rectifiers, and then the process deviationscan be depressed efectively. Taking into account the nonlinearity and static current ofthe rectifiers, we propose an accurate approximation model of the received signal strengthindicator’s transfer function, and provide a design flow of received signal strength indica-tors assisted by the proposed model. In addition, we proposed an active-RC demodulationscheme for gauss frequency shift keying, and the scheme has the advantages of low powerand a large dynamic range.
引文
[1] Naik R, Le H P, Singh J, et al. Potential of Reconfigurable Digital Backend in UWB Receiverfor Wireless Sensor Network. Proceedings of International Conference on Intelligent Sensors,Sensor Networks and Information (ISSNIP), Melbourne, Australia,2007.215–220.
[2] Enz C, Scolari N, Yodprasit U. Ultra low-power radio design for wireless sensor networks.Proceedings of IEEE International Workshop on Radio-Frequency Integration Technology: In-tegrated Circuits for Wideband Communication and Wireless Sensor Networks, Institute ofMicroelectronics, Singapore,2005.1–17.
[3] D E. Wireless sensor networks, part IV: sensor network protocols. Technical report, MobiCom,2002.
[4] Jri L, Chen Y, Yenlin H. A low-power low-cost fully-integrated60-GHz transceiver systemwith OOK modulation and on-board antenna assembly. IEEE Journal of Solid-State Circuits,2010,45(2):264–275.
[5] Juntunen E, Leung M C, Barale F, et al. A60-GHz38-pJ/bit3.5-Gb/s90-nm CMOS OOKdigital radio. IEEE Transactions on Microwave Theory and Techniques,2010,58(2):348–355.
[6] Pletcher N M, Gambini S, Rabaey J. A52μW wake-up receiver with-72dBm sensitivity usingan uncertain-IF architecture. IEEE Journal of Solid-State Circuits,2009,44(1):269–280.
[7] Porret A S, Melly T, Python D, et al. An ultralow-power UHF transceiver integrated in astandard digital CMOS process: architecture and receiver. IEEE Journal of Solid-State Circuits,2001,36(3):452–466.
[8] Melly T, Porret A S, Enz C C, et al. An ultralow-power UHF transceiver integrated in a standarddigital MOS process: transmitter. IEEE Journal of Solid-State Circuits,2001,36(3):467–472.
[9] Peiris V, Arm C, Bories S, et al. A1V433/868MHz25kb/s-FSK2kb/s-OOK RF transceiverSoC in standard digital0.18μm CMOS. Proceedings of IEEE International Solid-State CircuitsConference (ISSCC), Digest of Technical Papers, San Francisco, CA, USA,2005.258–259Vol.1.
[10] Quinlan P, Crowley P, Chanca M, et al. A multimode0.3-200-kb/s transceiver for the433/868/915-MHz bands in0.25-μm CMOS. IEEE Journal of Solid-State Circuits,2004,39(12):2297–2310.
[11] Wong A C, Kathiresan G, Chan C K, et al. A1V wireless transceiver for an ultra-low-powerSoC for biotelemetry applications. IEEE Journal of Solid-State Circuits,2008,43(7):1511–1521.
[12] Terada T, Yoshizumi S, Muqsith M, et al. A CMOS ultra-wideband impulse radio transceiverfor1-mb/s data communications and±2.5-cm range finding. IEEE Journal of Solid-StateCircuits,2006,41(4):891–898.
[13] LAN/MAN Standards Committee of the IEEE Computer Society. wireless medium accesscontrol (MAC) and physical layer (PHY) specifications for low rate wireless personal areanetworks (LR-WPANs), IEEE std.802.15.4.2003..
[14] Flatscher M, Dielacher M, Herndl T, et al. A bulk acoustic wave (BAW) based transceiverfor an in-tire-pressure monitoring sensor node. IEEE Journal of Solid-State Circuits,2010,45(1):167–177.
[15] Hancock T M, Straayer M, Messier A. A sub-10mW2Mbps BFSK transceiver at1.35to1.75GHz. Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Hon-olulu, Hawaii, USA,2007.97–100.
[16] Namjun C, Long Y, Joonsung B, et al. A60kb/s-10Mb/s adaptive frequency hoppingtransceiver for interference-resilient body channel communication. IEEE Journal of Solid-State Circuits,2009,44(3):708–717.
[17] Joonsung B, Hoi-Jun Y. A low energy injection-locked FSK transceiver with frequency-to-amplitude conversion for body sensor applications. Proceedings of IEEE Symposium on VLSICircuits (VLSIC), Honolulu, USA,2010.133–134.
[18] Huaide W, Meng-Hsiung H, Yu-Ching Y, et al. A60-GHz FSK transceiver with automatically-calibrated demodulator in90-nm CMOS. Proceedings of IEEE Symposium on VLSI Circuits(VLSIC), Honolulu, USA,2010.95–96.
[19] Rofougaran A, Chang G, Rael J J, et al. A single-chip900-MHz spread-spectrum wirelesstransceiver in1-μm CMOS. II. Receiver design. IEEE Journal of Solid-State Circuits,1998,33(4):535–547.
[20] Rofougaran A, Chang G, Rael J J, et al. A single-chip900-MHz spread-spectrum wirelesstransceiver in1-μm CMOS. I. Architecture and transmitter design. IEEE Journal of Solid-State Circuits,1998,33(4):515–534.
[21] Schuchter W, Krasser G, Schultheiss V, et al. A single chip FSK/ASK900MHz transceiverin a standard0.25μm CMOS technology. Proceedings of IEEE Radio Frequency IntegratedCircuits (RFIC) Symposium, Digest of Papers, Phoenix, Arizona, USA,2001.183–186.
[22] Bae J, Cho N, Yoo H J. A490μW fully MICS compatible FSK transceiver for implantabledevices. Proceedings of IEEE Symposium on VLSI Circuits (VLSIC), Kyoto, Japan,2009.36–37.
[23] Jerng A, Truong A, Wolday D, et al. Integrated CMOS transceivers using single-conversionstandard IF or low IF RX for digital narrowband cordless systems. Proceedings of IEEE RadioFrequency Integrated Circuits (RFIC) Symposium, Seattle, Washington, USA,2002.111–114.
[24] Nezhad-Ahmadi M R, Weale G, El-Agha A, et al. A2mW400MHz RF transceiver SoC in0.18μm CMOS technology for wireless medical applications. Proceedings of IEEE RadioFrequency Integrated Circuits (RFIC) Symposium, Atlanta, Georgia, USA,2008.285–288.
[25] van L R, van E M, van G D, et al. An ultra-low-power868/915MHz RF transceiver for wirelesssensor network applications. Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC)Symposium, Boston, MA, USA,2009.113–116.
[26] Perrott M H, Tewksbury T L, Sodini C G. A27-mW CMOS fractional-N synthesizer usingdigital compensation for2.5-Mb/s GFSK modulation. IEEE Journal of Solid-State Circuits,1997,32(12):2048–2060.
[27] Hegazi E, Abidi A A. A17-mW transmitter and frequency synthesizer for900-MHz GSM fullyintegrated in0.35-μm CMOS. IEEE Journal of Solid-State Circuits,2003,38(5):782–792.
[28] Kluge W, Poegel F, Roller H, et al. A fully integrated2.4-GHz IEEE802.15.4-compliant transceiver for ZigBeeT Mapplications. IEEE Journal of Solid-State Circuits,2006,41(12):2767–2775.
[29] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:231.
[30] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:274.
[31] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:177.
[32] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:333.
[33] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:323.
[34] Razavi B.射频微电子.清华大学出版社,北京,影印本第一版,2003:50.
[35] Nair M U, Yuanjin Z, Chyuen W A, et al. A low SIR impulse-UWB transceiver utilizing chirpFSK in0.18μm CMOS. IEEE Journal of Solid-State Circuits,2010,45(11):2388–2403.
[36] Yong-Sik Y, Jae-Hong C, Kwang-Jin K, et al. A2GHz16dBm IIP3low noise amplifier in0.25μm CMOS technology. Proceedings of IEEE International Solid-State Circuits Conference(ISSCC), Digest of Technical Papers, San Francisco, CA, USA,2003.452–507vol.1.
[37] Yongwang D, Harjani R. A+18dBm IIP3LNA in0.35μm CMOS. Proceedings of IEEE Inter-national Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco,CA, USA,2001.162–163,443.
[38] Kuhn W B, Mojarradi M M, Moussessian A. A resonant switch for LNA protection in watt-level CMOS transceivers. IEEE Transactions on Microwave Theory and Techniques,2005,53(9):2819–2825.
[39]张利.分数N频率合成器若干关键技术研究[申请清华大学工学博士论文].2007.
[40] Shaefer D, Lee T. A1.5-V,1.5-GHz CMOS low noise amplifier. IEEE Journal of Solid-StateCircuits,1997,32(5):745–759.
[41] Lee T H. CMOS射频集成电路设计.电子工业出版社,北京,英文版第二版,2005:420.
[42] Nguyen T K, Krizhanovskii V, Lee J, et al. A Low-Power RF Direct-Conversion Re-ceiver/Transmitter for2.4-GHz-Band IEEE802.15.4Standard in0.18-μm CMOS Technology.IEEE Transactions on Microwave Theory and Techniques,2006,54(12):4062–4071.
[43] Crols J, Steyaert M S. A1.5GHz highly linear CMOS downconversion mixer. IEEE Journalof Solid-State Circuits,1995,30(7):736–742.
[44] Valla M, Montagna G, Castello R, et al. A72-mW CMOS802.11a direct conversion front-endwith3.5-dB NF and200-kHz1/f noise corner. IEEE Journal of Solid-State Circuits,2005,40(4):970–977.
[45] Crols J, Steyaert M. An analog integrated polyphase filter for a high performance low-IFreceiver. Proceedings of IEEE Symposium on VLSI Circuits (VLSIC), Kyoto, Japan,1995.87–88.
[46] Annamalai A M, Kok F O, Yeung B C, et al. A2.4-GHz CMOS RF front-end for wirelesssensor network applications. Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC)Symposium, San Francisco, CA, USA,2006.4pp..
[47] Cook B W, Berny A, Molnar A, et al. Low-power2.4-GHz transceiver with passive RX front-end and400-mV supply. IEEE Journal of Solid-State Circuits,2006,41(12):2757–2766.
[48] Vaucher C S, Ferencic I, Locher M, et al. A family of low-power truly modular programmabledividers in standard0.35-μm CMOS technology. IEEE Journal of Solid-State Circuits,2000,35(7):1039–1045.
[49] Cao C, O K K. A power efcient26-GHz32:1static frequency divider in130-nm bulk CMOS.IEEE Microwave and Wireless Components Letters,2005,15(11):721–723.
[50] Yanping D, Kenneth K O. A21-GHz8-modulus prescaler and a20-GHz phase-locked loopfabricated in130-nm CMOS. IEEE Journal of Solid-State Circuits,2007,42(6):1240–1249.
[51] Pellerano S, Levantino S, Samori C, et al. A13.5-mW5-GHz frequency synthesizer withdynamic-logic frequency divider. IEEE Journal of Solid-State Circuits,2004,39(2):378–383.
[52] Fan-Hsiu H, Yi-Jen C. V-band CMOS diferential-type injection locked frequency dividers.Proceedings of International Symposium on VLSI Design, Automation and Test, Hsinchu,Taiwan,2006.1–2.
[53] Cheng S, Tong H, Silva-Martinez J, et al. A fully diferential low-power divide-by-8injection-locked frequency divider up to18GHz. IEEE Journal of Solid-State Circuits,2007,42(3):583–591.
[54] Ka F C, Cheng K K. Low power quadrature-input programmable frequency divider. Proceed-ings of Asia-Pacific Microwave Conference, Hong Kong, China,2008.1–4.
[55] Yueh-Hua Y, Chen Y J. Ring-based direct injection-locked frequency divider in display tech-nology. IEEE Microwave and Wireless Components Letters,2008,18(11):752–754.
[56] Zheng H, Luong H C. Ultra-low-voltage20-GHz frequency dividers using transformer feed-back in0.18-μm CMOS process. IEEE Journal of Solid-State Circuits,2008,43(10):2293–2302.
[57] Razavi B.射频微电子.清华大学出版社,北京,影印本第一版,2003:15.
[58] Kundert K S. Introduction to RF simulation and its application. IEEE Journal of Solid-StateCircuits,1999,34(9):1298–1319.
[59] Wilingham S, Perrott M, Setterberg B, et al. An integrated2.5GHz Σ frequency synthe-sizer with5μs settling and2Mb/s closed loop modulation. Proceedings of IEEE Interna-tional Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco,CA, USA,2000.200–201,457.
[60] McMahill D R, Sodini C G. A2.5-Mb/s GFSK5.0-Mb/s4-FSK automatically calibrated Σfrequency synthesizer. IEEE Journal of Solid-State Circuits,2002,37(1):18–26.
[61] Peng K C, Huang C H, Li C J, et al. Design of a CMOS VCO with two tuning inputs applied fora wideband GFSK-modulated frequency synthesizer. Proceedings of IEEE Radio and WirelessSymposium, San Diego, CA, USA,2006.443–446.
[62] Yao-Hong L, Tsung-Hsien L. An energy-efcient1.5-Mbps wireless FSK transmitter witha Σ modulated phase rotator. Proceedings of Proceeding of European Solid-State CircuitsConference (ESSCIRC), Munich, Germany,2007.488–491.
[63] Ferriss M A, Flynn M P. A14mW fractional-N PLL modulator with a digital phase detectorand frequency switching scheme. IEEE Journal of Solid-State Circuits,2008,43(11):2464–2471.
[64] Rahajandraibe W, Zaid L, Cheynet B V, et al. Frequency synthesizer and FSK modulator forIEEE802.15.4based applications. Proceedings of IEEE Radio Frequency Integrated Circuits(RFIC) Symposium, Honolulu, Hawaii, USA,2007.229–232.
[65] Hanil L, Mohammadi S. A subthreshold low phase noise CMOS LC VCO for ultra low powerapplications. IEEE Microwave and Wireless Components Letters,2007,17(11):796–798.
[66] Shuenn-Yuh L, Jian-Yu H. Analysis and implementation of a0.9-V voltage-controlled os-cillator with low phase noise and low power dissipation. IEEE Transactions on Circuits andSystems II: Express Briefs,2008,55(7):624–627.
[67] Yu-Lung L, Wei-Bin Y, Ting-Sheng C, et al. Designing an ultra low-voltage phase-locked loopusing a bulk-driven technique. IEEE Transactions on Circuits and Systems II: Express Briefs,2009,56(5):339–343.
[68] Sheng-Lyang J, Chuang-Jen H, Ching-Wen H, et al. A0.3V cross-coupled VCO usingdynamic threshold MOSFET. IEEE Microwave and Wireless Components Letters,2010,20(3):166–168.
[69] Craninckx J, Steyaert M S. A1.8-GHz CMOS low-phase-noise voltage-controlled oscillatorwith prescaler. IEEE Journal of Solid-State Circuits,1995,30(12):1474–1482.
[70] Geum-Young T, Seok-Bong H, Tae Y K, et al. A6.3-9-GHz CMOS fast settling PLL forMB-OFDM UWB applications. IEEE Journal of Solid-State Circuits,2005,40(8):1671–1679.
[71] Ng A W, Leung G C, Ka-Chun K, et al. A1-V24-GHz17.5-mW phase-locked loop in a0.18-μm CMOS process. IEEE Journal of Solid-State Circuits,2006,41(6):1236–1244.
[72] Dongmin P, SeongHwan C. A1.8V900μW4.5GHz VCO and prescaler in0.18μm CMOSusing charge-recycling technique. IEEE Microwave and Wireless Components Letters,2009,19(2):104–106.
[73] Woo K, Ham D. Fast-locking integer/fractional-N hybrid PLL frequency synthesizer. Pro-ceedings of IEEE International Midwest Symposium on Circuits and Systems, Puerto Rico,volume1,2006.674–678,.
[74] Xiaofei K, Nanjian W. A fast-settling PLL frequency synthesizer with direct frequency preset-ting. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), Digest ofTechnical Papers, San Francisco, CA, USA,2006.741–750.
[75] Swaminathan A, Wang K J, Galton I. A wide-bandwidth2.4GHz ISM band fractional-N PLL with adaptive phase noise cancellation. IEEE Journal of Solid-State Circuits,2007,42(12):2639–2650.
[76] Ting W, Hanumolu P K, Mayaram K, et al. A4.2GHz PLL frequency synthesizer with anadaptively tuned coarse loop. Proceedings of IEEE Custom Integrated Circuits Conference(CICC), San Jose, CA,2007.547–550.
[77] Chiu W H, Huang Y H, Lin T H. A5GHz phase-locked loop using dynamic phase-errorcompensation technique for fast settling in0.18-μm CMOS. Proceedings of IEEE Symposiumon VLSI Circuits (VLSIC), Kyoto, Japan,2009.128–129.
[78] Chi-Sheng L, Ting-Hsu C, Chin-Long W, et al. An edge missing compensator for fast set-tling wide locking range phase-locked loops. IEEE Journal of Solid-State Circuits,2009,44(11):3102–3110.
[79] Yu-Jen L, Tsung-Hsien L. A10-GHz CMOS PLL with an agile VCO calibration. Proceedingsof Asian Solid-State Circuits Conference, Hsinchu, Taiwa.213–216.
[80] Yue-Fang K, Ro-Min W, Chuan-Yu L. A fast locking PLL with phase error detector. Proceed-ings of IEEE Conference on Electron Devices and Solid-State Circuits, Hong Kong, China,2005.423–426.
[81] Zhao B, Mao X, Yang H, et al. A voltage-controlled oscillator with an ultra-low supply voltageand its application to a fractional-N phase-locked loop. International Journal of Electronics,2009,96(10):1011–1022.
[82] Leeson D B. A simple model of feedback oscillator noise spectrum. Proceedings of the IEEE,1966,54(2):329–330.
[83] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:83.
[84]沈维伦,杨雨佳,王方林, et al.用于蓝牙芯片的高斯滤波移频键控.固体电子学研究与进展,2006,26(3).
[85] Galton I. Delta-sigma fractional-N phase-locked loops. Phase-locking in high-performancesystems: from device to architectures, Hoboken, NJ: Wiley-Interscience,2003.
[86] Herzel F, Osmany S A, Scheytt J C. Analytical phase-noise modeling and charge pump opti-mization for fractional-N PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers,2010,57(8):1914–1924.
[87] Kun-Seok L, Hwayeal Y, Hyung K A, et al. A0.13-μm CMOS Σ-frequencysynthesizer with an area optimizing LPF, fast AFC time, and a wideband VCO forWCDMA/GSM/GPRS/EDGE applications. Proceedings of IEEE Radio Frequency IntegratedCircuits (RFIC) Symposium, Atlanta, Georgia, USA,2008.299–302.
[88]冒小建. Sigma-Delta分数分频锁相环频率合成器的分析与设计[申请清华大学工学博士论文].2006.
[89] Craninckx J, Steyaert M S. A1.75-GHz/3-V dual-modulus divide-by-128/129prescaler in0.7-μm CMOS. IEEE Journal of Solid-State Circuits,1996,31(7):890–897.
[90] Shu K, Sanchez-Sinencio E. A5-GHz prescaler using improved phase switching. Proceed-ings of IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona,volume3,2002. III–85–III–88.
[91] Hung C M, Floyd B, Park N, et al. Fully integrated5.35-GHz CMOS VCOs and prescalers.IEEE Transactions on Microwave Theory and Techniques,2001,49(1):17–22.
[92] Si W W, Mehta S, Samavati H, et al. A1.9-GHz single-chip CMOS PHS cellphone. IEEEJournal of Solid-State Circuits,2006,41(12):2737–2745.
[93] Kyoungho W, Yong L, Eunsoo N, et al. Fast-lock hybrid PLL combining fractional-Nand integer-N modes of difering bandwidths. IEEE Journal of Solid-State Circuits,2008,43(2):379–389.
[94] Shin J, Shin H. A fast and high-precision VCO frequency calibration technique for widebandΣ fractional-N frequency synthesizers. IEEE Transactions on Circuits and Systems I: RegularPapers,2010,57(7):1573–1582.
[95] Wei-Hao C, Yu-Hsiang H, Tsung-Hsien L. A dynamic phase error compensation technique forfast-locking phase-locked loops. IEEE Journal of Solid-State Circuits,2010,45(6):1137–1149.
[96] Sun Y, Yu X, Rhee W, et al. A fast settling dual-path fractional-N PLL with hybrid-modedynamic bandwidth control. IEEE Microwave and Wireless Components Letters,2010,20(8):462–464.
[97] Shon-Hang W, Chao-Shiun W, Chorng-Kuang W. A low power20GHz1.5Gb/s CMOSinjection-pulling FSK modulator and frequency discriminator for60GHz links. Proceedingsof IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA,2008.483–486.
[98] Chao-Shiun W, Kun-Da C, Chorng-Kuang W. A0.13μm CMOS2.5Gb/s FSK demodulatorusing injection-locked technique. Proceedings of IEEE Radio Frequency Integrated CircuitsSymposium (RFIC), Boston, MA, USA,2009.563–566.
[99] Komurasaki H, Sato H, Ono M, et al. A single-chip2.4-GHz RF transceiver LSI with a wide-input-range frequency discriminator. IEICE Transactions on Electronics, PAPER,2002, E85-C(7):1419–1427.
[100] Li-Shin L, Hsieh-Hung H, Po-Shuan W, et al. An experimental ultra-low-voltage demodu-lator in0.18-μm CMOS. IEEE Transactions on Microwave Theory and Techniques,2009,57(10):2307–2317.
[101] Hong-Sing K, Ming-Jen Y, Tai-Cheng L. A delay-line-based GFSK demodulator for low-IF re-ceivers. Proceedings of International Solid-State Circuits Conference (ISSCC), San Francisco,CA, USA,2007.88–589.
[102] Tai-Cheng L, Chin-Chi C. A mixed-signal GFSK demodulator for Bluetooth. IEEE Transac-tions on Circuits and Systems II: Express Briefs[see also Circuits and Systems II: Analog andDigital Signal Processing,2006,53(3):197–201.
[103] Komurasaki H, Sato H, Ono M, et al. A single-chip2.4GHz RF transceiver LSI with a wide-range FV conversion demodulator. Proceedings of IEEE International Solid-State CircuitsConference (ISSCC), Digest of Technical Papers, San Francisco, CA, USA,2001.206–207,448.
[104] Gustat H, Herzel F. Integrated FSK demodulator with very high sensitivity. IEEE Journal ofSolid-State Circuits,2003,38(2):357–360.
[105] Yi-Chung C, Yi-Chang W, Po-Chiun H. A1.2-V CMOS limiter/RSSI/demodulator for low-IF FSK receiver. Proceedings of IEEE Custom Integrated Circuits Conference (CICC), SanJose, CA, USA,2007.217–220.
[106] Wenjun S, Bo X, Emira A, et al. A monolithic CMOS low-IF Bluetooth receiver. Proceedingsof IEEE Custom Integrated Circuits Conference (CICC), Orlando, Florida, USA,2002.247–250.
[107] Chia-Pei C, Simon C L, Hong-Sing K, et al. A single-chip low-power tunable CMOS low-IF single-conversion ISM receiver. Proceedings of Asian Solid-State Circuits Conference(ASSCC), Hsinchu, Taiwan,2005.337–340.
[108] Darabi H, Khorram S, Ibrahim B, et al. An IF FSK demodulator for Bluetooth in0.35μmCMOS. Proceedings of IEEE Conference on Custom Integrated Circuits (CICC), San Diego,California, USA,2001.523–526.
[109] Chun-Pang W, Hen-Wai T. A110-MHz84-dB CMOS programmable gain amplifier withintegrated RSSI function. IEEE Journal of Solid-State Circuits,2005,40(6):1249–1258.
[110] Chien-Chih L, Kuang-Hu H, Chorng-Kuang W. A15mW280MHz80dB gain CMOS limit-ing/logarithmic amplifier with active cascode gain-enhancement. Proceedings of Proceedingsof European Solid-State Circuits Conference (ESSCIRC), Firenze, Italy,2002.311–314.
[111] Chao Y, Mason A. Precise RSSI with high process variation tolerance. Proceedings of IEEEInternational Symposium on Circuits and Systems (ISCAS), New Orleans, Louisiana, USA,2007.2870–2873.
[112] Wei-Yi H, Jia-Wei L, Kuo-Chi T, et al. An RF transceiver with auto signal detection andcombined PGA/RSSI in0.18μm CMOS for V2.1Bluetooth applications. Proceedings of IEEERadio Frequency Integrated Circuits (RFIC) Symposium, Boston, Massachusetts, USA,2009.109–112.
[113] Po-Chiun H, Yi-Huei C, Chorng-Kuang W. A2-V10.7-MHz CMOS limiting amplifier/RSSI.IEEE Journal of Solid-State Circuits,2000,35(10):1474–1480.
[114] Hong-Sun K, Ismail M, Olsson H. CMOS limiters with RSSIs for Bluetooth receivers. Pro-ceedings of IEEE Midwest Symposium on Circuits and Systems, Dayton, Ohio, USA,2001.812–815vol.2.
[115] Harjani R, Birkenes O, Kim J. An IF stage design for an ASK-based wireless telemetry system.Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Geneva,Switzerland,2000.52–55vol.1.
[116] Razavi B.射频微电子.清华大学出版社,北京,影印本第一版,2003:16.
[117]姚金科.适用于短距离无线通信的中频接收电路关键技术研究[申请清华大学工学博士论文].2007.
[118] T H T, M A A, Wooi G Y, et al. A90nm CMOS variable-gain amplifier and RSSI design forwide-band wireless network application. Proceedings of Proceedings of European Solid-StateCircuits Conference (ESSCIRC), Montreux, Switzerland,2006.86–89.
[2] Enz C, Scolari N, Yodprasit U. Ultra low-power radio design for wireless sensor networks.Proceedings of IEEE International Workshop on Radio-Frequency Integration Technology: In-tegrated Circuits for Wideband Communication and Wireless Sensor Networks, Institute ofMicroelectronics, Singapore,2005.1–17.
[3] D E. Wireless sensor networks, part IV: sensor network protocols. Technical report, MobiCom,2002.
[4] Jri L, Chen Y, Yenlin H. A low-power low-cost fully-integrated60-GHz transceiver systemwith OOK modulation and on-board antenna assembly. IEEE Journal of Solid-State Circuits,2010,45(2):264–275.
[5] Juntunen E, Leung M C, Barale F, et al. A60-GHz38-pJ/bit3.5-Gb/s90-nm CMOS OOKdigital radio. IEEE Transactions on Microwave Theory and Techniques,2010,58(2):348–355.
[6] Pletcher N M, Gambini S, Rabaey J. A52μW wake-up receiver with-72dBm sensitivity usingan uncertain-IF architecture. IEEE Journal of Solid-State Circuits,2009,44(1):269–280.
[7] Porret A S, Melly T, Python D, et al. An ultralow-power UHF transceiver integrated in astandard digital CMOS process: architecture and receiver. IEEE Journal of Solid-State Circuits,2001,36(3):452–466.
[8] Melly T, Porret A S, Enz C C, et al. An ultralow-power UHF transceiver integrated in a standarddigital MOS process: transmitter. IEEE Journal of Solid-State Circuits,2001,36(3):467–472.
[9] Peiris V, Arm C, Bories S, et al. A1V433/868MHz25kb/s-FSK2kb/s-OOK RF transceiverSoC in standard digital0.18μm CMOS. Proceedings of IEEE International Solid-State CircuitsConference (ISSCC), Digest of Technical Papers, San Francisco, CA, USA,2005.258–259Vol.1.
[10] Quinlan P, Crowley P, Chanca M, et al. A multimode0.3-200-kb/s transceiver for the433/868/915-MHz bands in0.25-μm CMOS. IEEE Journal of Solid-State Circuits,2004,39(12):2297–2310.
[11] Wong A C, Kathiresan G, Chan C K, et al. A1V wireless transceiver for an ultra-low-powerSoC for biotelemetry applications. IEEE Journal of Solid-State Circuits,2008,43(7):1511–1521.
[12] Terada T, Yoshizumi S, Muqsith M, et al. A CMOS ultra-wideband impulse radio transceiverfor1-mb/s data communications and±2.5-cm range finding. IEEE Journal of Solid-StateCircuits,2006,41(4):891–898.
[13] LAN/MAN Standards Committee of the IEEE Computer Society. wireless medium accesscontrol (MAC) and physical layer (PHY) specifications for low rate wireless personal areanetworks (LR-WPANs), IEEE std.802.15.4.2003..
[14] Flatscher M, Dielacher M, Herndl T, et al. A bulk acoustic wave (BAW) based transceiverfor an in-tire-pressure monitoring sensor node. IEEE Journal of Solid-State Circuits,2010,45(1):167–177.
[15] Hancock T M, Straayer M, Messier A. A sub-10mW2Mbps BFSK transceiver at1.35to1.75GHz. Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Hon-olulu, Hawaii, USA,2007.97–100.
[16] Namjun C, Long Y, Joonsung B, et al. A60kb/s-10Mb/s adaptive frequency hoppingtransceiver for interference-resilient body channel communication. IEEE Journal of Solid-State Circuits,2009,44(3):708–717.
[17] Joonsung B, Hoi-Jun Y. A low energy injection-locked FSK transceiver with frequency-to-amplitude conversion for body sensor applications. Proceedings of IEEE Symposium on VLSICircuits (VLSIC), Honolulu, USA,2010.133–134.
[18] Huaide W, Meng-Hsiung H, Yu-Ching Y, et al. A60-GHz FSK transceiver with automatically-calibrated demodulator in90-nm CMOS. Proceedings of IEEE Symposium on VLSI Circuits(VLSIC), Honolulu, USA,2010.95–96.
[19] Rofougaran A, Chang G, Rael J J, et al. A single-chip900-MHz spread-spectrum wirelesstransceiver in1-μm CMOS. II. Receiver design. IEEE Journal of Solid-State Circuits,1998,33(4):535–547.
[20] Rofougaran A, Chang G, Rael J J, et al. A single-chip900-MHz spread-spectrum wirelesstransceiver in1-μm CMOS. I. Architecture and transmitter design. IEEE Journal of Solid-State Circuits,1998,33(4):515–534.
[21] Schuchter W, Krasser G, Schultheiss V, et al. A single chip FSK/ASK900MHz transceiverin a standard0.25μm CMOS technology. Proceedings of IEEE Radio Frequency IntegratedCircuits (RFIC) Symposium, Digest of Papers, Phoenix, Arizona, USA,2001.183–186.
[22] Bae J, Cho N, Yoo H J. A490μW fully MICS compatible FSK transceiver for implantabledevices. Proceedings of IEEE Symposium on VLSI Circuits (VLSIC), Kyoto, Japan,2009.36–37.
[23] Jerng A, Truong A, Wolday D, et al. Integrated CMOS transceivers using single-conversionstandard IF or low IF RX for digital narrowband cordless systems. Proceedings of IEEE RadioFrequency Integrated Circuits (RFIC) Symposium, Seattle, Washington, USA,2002.111–114.
[24] Nezhad-Ahmadi M R, Weale G, El-Agha A, et al. A2mW400MHz RF transceiver SoC in0.18μm CMOS technology for wireless medical applications. Proceedings of IEEE RadioFrequency Integrated Circuits (RFIC) Symposium, Atlanta, Georgia, USA,2008.285–288.
[25] van L R, van E M, van G D, et al. An ultra-low-power868/915MHz RF transceiver for wirelesssensor network applications. Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC)Symposium, Boston, MA, USA,2009.113–116.
[26] Perrott M H, Tewksbury T L, Sodini C G. A27-mW CMOS fractional-N synthesizer usingdigital compensation for2.5-Mb/s GFSK modulation. IEEE Journal of Solid-State Circuits,1997,32(12):2048–2060.
[27] Hegazi E, Abidi A A. A17-mW transmitter and frequency synthesizer for900-MHz GSM fullyintegrated in0.35-μm CMOS. IEEE Journal of Solid-State Circuits,2003,38(5):782–792.
[28] Kluge W, Poegel F, Roller H, et al. A fully integrated2.4-GHz IEEE802.15.4-compliant transceiver for ZigBeeT Mapplications. IEEE Journal of Solid-State Circuits,2006,41(12):2767–2775.
[29] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:231.
[30] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:274.
[31] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:177.
[32] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:333.
[33] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:323.
[34] Razavi B.射频微电子.清华大学出版社,北京,影印本第一版,2003:50.
[35] Nair M U, Yuanjin Z, Chyuen W A, et al. A low SIR impulse-UWB transceiver utilizing chirpFSK in0.18μm CMOS. IEEE Journal of Solid-State Circuits,2010,45(11):2388–2403.
[36] Yong-Sik Y, Jae-Hong C, Kwang-Jin K, et al. A2GHz16dBm IIP3low noise amplifier in0.25μm CMOS technology. Proceedings of IEEE International Solid-State Circuits Conference(ISSCC), Digest of Technical Papers, San Francisco, CA, USA,2003.452–507vol.1.
[37] Yongwang D, Harjani R. A+18dBm IIP3LNA in0.35μm CMOS. Proceedings of IEEE Inter-national Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco,CA, USA,2001.162–163,443.
[38] Kuhn W B, Mojarradi M M, Moussessian A. A resonant switch for LNA protection in watt-level CMOS transceivers. IEEE Transactions on Microwave Theory and Techniques,2005,53(9):2819–2825.
[39]张利.分数N频率合成器若干关键技术研究[申请清华大学工学博士论文].2007.
[40] Shaefer D, Lee T. A1.5-V,1.5-GHz CMOS low noise amplifier. IEEE Journal of Solid-StateCircuits,1997,32(5):745–759.
[41] Lee T H. CMOS射频集成电路设计.电子工业出版社,北京,英文版第二版,2005:420.
[42] Nguyen T K, Krizhanovskii V, Lee J, et al. A Low-Power RF Direct-Conversion Re-ceiver/Transmitter for2.4-GHz-Band IEEE802.15.4Standard in0.18-μm CMOS Technology.IEEE Transactions on Microwave Theory and Techniques,2006,54(12):4062–4071.
[43] Crols J, Steyaert M S. A1.5GHz highly linear CMOS downconversion mixer. IEEE Journalof Solid-State Circuits,1995,30(7):736–742.
[44] Valla M, Montagna G, Castello R, et al. A72-mW CMOS802.11a direct conversion front-endwith3.5-dB NF and200-kHz1/f noise corner. IEEE Journal of Solid-State Circuits,2005,40(4):970–977.
[45] Crols J, Steyaert M. An analog integrated polyphase filter for a high performance low-IFreceiver. Proceedings of IEEE Symposium on VLSI Circuits (VLSIC), Kyoto, Japan,1995.87–88.
[46] Annamalai A M, Kok F O, Yeung B C, et al. A2.4-GHz CMOS RF front-end for wirelesssensor network applications. Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC)Symposium, San Francisco, CA, USA,2006.4pp..
[47] Cook B W, Berny A, Molnar A, et al. Low-power2.4-GHz transceiver with passive RX front-end and400-mV supply. IEEE Journal of Solid-State Circuits,2006,41(12):2757–2766.
[48] Vaucher C S, Ferencic I, Locher M, et al. A family of low-power truly modular programmabledividers in standard0.35-μm CMOS technology. IEEE Journal of Solid-State Circuits,2000,35(7):1039–1045.
[49] Cao C, O K K. A power efcient26-GHz32:1static frequency divider in130-nm bulk CMOS.IEEE Microwave and Wireless Components Letters,2005,15(11):721–723.
[50] Yanping D, Kenneth K O. A21-GHz8-modulus prescaler and a20-GHz phase-locked loopfabricated in130-nm CMOS. IEEE Journal of Solid-State Circuits,2007,42(6):1240–1249.
[51] Pellerano S, Levantino S, Samori C, et al. A13.5-mW5-GHz frequency synthesizer withdynamic-logic frequency divider. IEEE Journal of Solid-State Circuits,2004,39(2):378–383.
[52] Fan-Hsiu H, Yi-Jen C. V-band CMOS diferential-type injection locked frequency dividers.Proceedings of International Symposium on VLSI Design, Automation and Test, Hsinchu,Taiwan,2006.1–2.
[53] Cheng S, Tong H, Silva-Martinez J, et al. A fully diferential low-power divide-by-8injection-locked frequency divider up to18GHz. IEEE Journal of Solid-State Circuits,2007,42(3):583–591.
[54] Ka F C, Cheng K K. Low power quadrature-input programmable frequency divider. Proceed-ings of Asia-Pacific Microwave Conference, Hong Kong, China,2008.1–4.
[55] Yueh-Hua Y, Chen Y J. Ring-based direct injection-locked frequency divider in display tech-nology. IEEE Microwave and Wireless Components Letters,2008,18(11):752–754.
[56] Zheng H, Luong H C. Ultra-low-voltage20-GHz frequency dividers using transformer feed-back in0.18-μm CMOS process. IEEE Journal of Solid-State Circuits,2008,43(10):2293–2302.
[57] Razavi B.射频微电子.清华大学出版社,北京,影印本第一版,2003:15.
[58] Kundert K S. Introduction to RF simulation and its application. IEEE Journal of Solid-StateCircuits,1999,34(9):1298–1319.
[59] Wilingham S, Perrott M, Setterberg B, et al. An integrated2.5GHz Σ frequency synthe-sizer with5μs settling and2Mb/s closed loop modulation. Proceedings of IEEE Interna-tional Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco,CA, USA,2000.200–201,457.
[60] McMahill D R, Sodini C G. A2.5-Mb/s GFSK5.0-Mb/s4-FSK automatically calibrated Σfrequency synthesizer. IEEE Journal of Solid-State Circuits,2002,37(1):18–26.
[61] Peng K C, Huang C H, Li C J, et al. Design of a CMOS VCO with two tuning inputs applied fora wideband GFSK-modulated frequency synthesizer. Proceedings of IEEE Radio and WirelessSymposium, San Diego, CA, USA,2006.443–446.
[62] Yao-Hong L, Tsung-Hsien L. An energy-efcient1.5-Mbps wireless FSK transmitter witha Σ modulated phase rotator. Proceedings of Proceeding of European Solid-State CircuitsConference (ESSCIRC), Munich, Germany,2007.488–491.
[63] Ferriss M A, Flynn M P. A14mW fractional-N PLL modulator with a digital phase detectorand frequency switching scheme. IEEE Journal of Solid-State Circuits,2008,43(11):2464–2471.
[64] Rahajandraibe W, Zaid L, Cheynet B V, et al. Frequency synthesizer and FSK modulator forIEEE802.15.4based applications. Proceedings of IEEE Radio Frequency Integrated Circuits(RFIC) Symposium, Honolulu, Hawaii, USA,2007.229–232.
[65] Hanil L, Mohammadi S. A subthreshold low phase noise CMOS LC VCO for ultra low powerapplications. IEEE Microwave and Wireless Components Letters,2007,17(11):796–798.
[66] Shuenn-Yuh L, Jian-Yu H. Analysis and implementation of a0.9-V voltage-controlled os-cillator with low phase noise and low power dissipation. IEEE Transactions on Circuits andSystems II: Express Briefs,2008,55(7):624–627.
[67] Yu-Lung L, Wei-Bin Y, Ting-Sheng C, et al. Designing an ultra low-voltage phase-locked loopusing a bulk-driven technique. IEEE Transactions on Circuits and Systems II: Express Briefs,2009,56(5):339–343.
[68] Sheng-Lyang J, Chuang-Jen H, Ching-Wen H, et al. A0.3V cross-coupled VCO usingdynamic threshold MOSFET. IEEE Microwave and Wireless Components Letters,2010,20(3):166–168.
[69] Craninckx J, Steyaert M S. A1.8-GHz CMOS low-phase-noise voltage-controlled oscillatorwith prescaler. IEEE Journal of Solid-State Circuits,1995,30(12):1474–1482.
[70] Geum-Young T, Seok-Bong H, Tae Y K, et al. A6.3-9-GHz CMOS fast settling PLL forMB-OFDM UWB applications. IEEE Journal of Solid-State Circuits,2005,40(8):1671–1679.
[71] Ng A W, Leung G C, Ka-Chun K, et al. A1-V24-GHz17.5-mW phase-locked loop in a0.18-μm CMOS process. IEEE Journal of Solid-State Circuits,2006,41(6):1236–1244.
[72] Dongmin P, SeongHwan C. A1.8V900μW4.5GHz VCO and prescaler in0.18μm CMOSusing charge-recycling technique. IEEE Microwave and Wireless Components Letters,2009,19(2):104–106.
[73] Woo K, Ham D. Fast-locking integer/fractional-N hybrid PLL frequency synthesizer. Pro-ceedings of IEEE International Midwest Symposium on Circuits and Systems, Puerto Rico,volume1,2006.674–678,.
[74] Xiaofei K, Nanjian W. A fast-settling PLL frequency synthesizer with direct frequency preset-ting. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), Digest ofTechnical Papers, San Francisco, CA, USA,2006.741–750.
[75] Swaminathan A, Wang K J, Galton I. A wide-bandwidth2.4GHz ISM band fractional-N PLL with adaptive phase noise cancellation. IEEE Journal of Solid-State Circuits,2007,42(12):2639–2650.
[76] Ting W, Hanumolu P K, Mayaram K, et al. A4.2GHz PLL frequency synthesizer with anadaptively tuned coarse loop. Proceedings of IEEE Custom Integrated Circuits Conference(CICC), San Jose, CA,2007.547–550.
[77] Chiu W H, Huang Y H, Lin T H. A5GHz phase-locked loop using dynamic phase-errorcompensation technique for fast settling in0.18-μm CMOS. Proceedings of IEEE Symposiumon VLSI Circuits (VLSIC), Kyoto, Japan,2009.128–129.
[78] Chi-Sheng L, Ting-Hsu C, Chin-Long W, et al. An edge missing compensator for fast set-tling wide locking range phase-locked loops. IEEE Journal of Solid-State Circuits,2009,44(11):3102–3110.
[79] Yu-Jen L, Tsung-Hsien L. A10-GHz CMOS PLL with an agile VCO calibration. Proceedingsof Asian Solid-State Circuits Conference, Hsinchu, Taiwa.213–216.
[80] Yue-Fang K, Ro-Min W, Chuan-Yu L. A fast locking PLL with phase error detector. Proceed-ings of IEEE Conference on Electron Devices and Solid-State Circuits, Hong Kong, China,2005.423–426.
[81] Zhao B, Mao X, Yang H, et al. A voltage-controlled oscillator with an ultra-low supply voltageand its application to a fractional-N phase-locked loop. International Journal of Electronics,2009,96(10):1011–1022.
[82] Leeson D B. A simple model of feedback oscillator noise spectrum. Proceedings of the IEEE,1966,54(2):329–330.
[83] Gu Q. RF System Design of Transceivers for Wireless Communications. New York, USA,Springer Science+Business Media, LLC,2005:83.
[84]沈维伦,杨雨佳,王方林, et al.用于蓝牙芯片的高斯滤波移频键控.固体电子学研究与进展,2006,26(3).
[85] Galton I. Delta-sigma fractional-N phase-locked loops. Phase-locking in high-performancesystems: from device to architectures, Hoboken, NJ: Wiley-Interscience,2003.
[86] Herzel F, Osmany S A, Scheytt J C. Analytical phase-noise modeling and charge pump opti-mization for fractional-N PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers,2010,57(8):1914–1924.
[87] Kun-Seok L, Hwayeal Y, Hyung K A, et al. A0.13-μm CMOS Σ-frequencysynthesizer with an area optimizing LPF, fast AFC time, and a wideband VCO forWCDMA/GSM/GPRS/EDGE applications. Proceedings of IEEE Radio Frequency IntegratedCircuits (RFIC) Symposium, Atlanta, Georgia, USA,2008.299–302.
[88]冒小建. Sigma-Delta分数分频锁相环频率合成器的分析与设计[申请清华大学工学博士论文].2006.
[89] Craninckx J, Steyaert M S. A1.75-GHz/3-V dual-modulus divide-by-128/129prescaler in0.7-μm CMOS. IEEE Journal of Solid-State Circuits,1996,31(7):890–897.
[90] Shu K, Sanchez-Sinencio E. A5-GHz prescaler using improved phase switching. Proceed-ings of IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona,volume3,2002. III–85–III–88.
[91] Hung C M, Floyd B, Park N, et al. Fully integrated5.35-GHz CMOS VCOs and prescalers.IEEE Transactions on Microwave Theory and Techniques,2001,49(1):17–22.
[92] Si W W, Mehta S, Samavati H, et al. A1.9-GHz single-chip CMOS PHS cellphone. IEEEJournal of Solid-State Circuits,2006,41(12):2737–2745.
[93] Kyoungho W, Yong L, Eunsoo N, et al. Fast-lock hybrid PLL combining fractional-Nand integer-N modes of difering bandwidths. IEEE Journal of Solid-State Circuits,2008,43(2):379–389.
[94] Shin J, Shin H. A fast and high-precision VCO frequency calibration technique for widebandΣ fractional-N frequency synthesizers. IEEE Transactions on Circuits and Systems I: RegularPapers,2010,57(7):1573–1582.
[95] Wei-Hao C, Yu-Hsiang H, Tsung-Hsien L. A dynamic phase error compensation technique forfast-locking phase-locked loops. IEEE Journal of Solid-State Circuits,2010,45(6):1137–1149.
[96] Sun Y, Yu X, Rhee W, et al. A fast settling dual-path fractional-N PLL with hybrid-modedynamic bandwidth control. IEEE Microwave and Wireless Components Letters,2010,20(8):462–464.
[97] Shon-Hang W, Chao-Shiun W, Chorng-Kuang W. A low power20GHz1.5Gb/s CMOSinjection-pulling FSK modulator and frequency discriminator for60GHz links. Proceedingsof IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA,2008.483–486.
[98] Chao-Shiun W, Kun-Da C, Chorng-Kuang W. A0.13μm CMOS2.5Gb/s FSK demodulatorusing injection-locked technique. Proceedings of IEEE Radio Frequency Integrated CircuitsSymposium (RFIC), Boston, MA, USA,2009.563–566.
[99] Komurasaki H, Sato H, Ono M, et al. A single-chip2.4-GHz RF transceiver LSI with a wide-input-range frequency discriminator. IEICE Transactions on Electronics, PAPER,2002, E85-C(7):1419–1427.
[100] Li-Shin L, Hsieh-Hung H, Po-Shuan W, et al. An experimental ultra-low-voltage demodu-lator in0.18-μm CMOS. IEEE Transactions on Microwave Theory and Techniques,2009,57(10):2307–2317.
[101] Hong-Sing K, Ming-Jen Y, Tai-Cheng L. A delay-line-based GFSK demodulator for low-IF re-ceivers. Proceedings of International Solid-State Circuits Conference (ISSCC), San Francisco,CA, USA,2007.88–589.
[102] Tai-Cheng L, Chin-Chi C. A mixed-signal GFSK demodulator for Bluetooth. IEEE Transac-tions on Circuits and Systems II: Express Briefs[see also Circuits and Systems II: Analog andDigital Signal Processing,2006,53(3):197–201.
[103] Komurasaki H, Sato H, Ono M, et al. A single-chip2.4GHz RF transceiver LSI with a wide-range FV conversion demodulator. Proceedings of IEEE International Solid-State CircuitsConference (ISSCC), Digest of Technical Papers, San Francisco, CA, USA,2001.206–207,448.
[104] Gustat H, Herzel F. Integrated FSK demodulator with very high sensitivity. IEEE Journal ofSolid-State Circuits,2003,38(2):357–360.
[105] Yi-Chung C, Yi-Chang W, Po-Chiun H. A1.2-V CMOS limiter/RSSI/demodulator for low-IF FSK receiver. Proceedings of IEEE Custom Integrated Circuits Conference (CICC), SanJose, CA, USA,2007.217–220.
[106] Wenjun S, Bo X, Emira A, et al. A monolithic CMOS low-IF Bluetooth receiver. Proceedingsof IEEE Custom Integrated Circuits Conference (CICC), Orlando, Florida, USA,2002.247–250.
[107] Chia-Pei C, Simon C L, Hong-Sing K, et al. A single-chip low-power tunable CMOS low-IF single-conversion ISM receiver. Proceedings of Asian Solid-State Circuits Conference(ASSCC), Hsinchu, Taiwan,2005.337–340.
[108] Darabi H, Khorram S, Ibrahim B, et al. An IF FSK demodulator for Bluetooth in0.35μmCMOS. Proceedings of IEEE Conference on Custom Integrated Circuits (CICC), San Diego,California, USA,2001.523–526.
[109] Chun-Pang W, Hen-Wai T. A110-MHz84-dB CMOS programmable gain amplifier withintegrated RSSI function. IEEE Journal of Solid-State Circuits,2005,40(6):1249–1258.
[110] Chien-Chih L, Kuang-Hu H, Chorng-Kuang W. A15mW280MHz80dB gain CMOS limit-ing/logarithmic amplifier with active cascode gain-enhancement. Proceedings of Proceedingsof European Solid-State Circuits Conference (ESSCIRC), Firenze, Italy,2002.311–314.
[111] Chao Y, Mason A. Precise RSSI with high process variation tolerance. Proceedings of IEEEInternational Symposium on Circuits and Systems (ISCAS), New Orleans, Louisiana, USA,2007.2870–2873.
[112] Wei-Yi H, Jia-Wei L, Kuo-Chi T, et al. An RF transceiver with auto signal detection andcombined PGA/RSSI in0.18μm CMOS for V2.1Bluetooth applications. Proceedings of IEEERadio Frequency Integrated Circuits (RFIC) Symposium, Boston, Massachusetts, USA,2009.109–112.
[113] Po-Chiun H, Yi-Huei C, Chorng-Kuang W. A2-V10.7-MHz CMOS limiting amplifier/RSSI.IEEE Journal of Solid-State Circuits,2000,35(10):1474–1480.
[114] Hong-Sun K, Ismail M, Olsson H. CMOS limiters with RSSIs for Bluetooth receivers. Pro-ceedings of IEEE Midwest Symposium on Circuits and Systems, Dayton, Ohio, USA,2001.812–815vol.2.
[115] Harjani R, Birkenes O, Kim J. An IF stage design for an ASK-based wireless telemetry system.Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Geneva,Switzerland,2000.52–55vol.1.
[116] Razavi B.射频微电子.清华大学出版社,北京,影印本第一版,2003:16.
[117]姚金科.适用于短距离无线通信的中频接收电路关键技术研究[申请清华大学工学博士论文].2007.
[118] T H T, M A A, Wooi G Y, et al. A90nm CMOS variable-gain amplifier and RSSI design forwide-band wireless network application. Proceedings of Proceedings of European Solid-StateCircuits Conference (ESSCIRC), Montreux, Switzerland,2006.86–89.