13位低功耗Sigma-Delta调制器的设计及其应用
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摘要
随着集成电路的飞速发展,模拟和数字之间的转换扮演着越来越重要的角色。在众多的ADC结构中,Sigma-Delta ADC利用过采样技术和噪声整形技术,不但提高了信噪比而且能够有效衰减输出信号带内的量化噪声,从而降低了功耗,与传统的Nyquist转换器相比,它降低了对模拟电路性能指标和元件精度的要求,简化了模拟电路的设计,降低了生产成本。目前在高精度音频带宽的Sigma-Delta ADC中存在较大的功耗(>10mW),对∑△ADC的深入研究和发展趋势上设计了精度为13位的低功耗调制器,具有330μW的功耗。
分析了调制器对量化噪声的整形作用,讨论了几种常见的Nyquist结构的ADC,比较了不同结构的Sigma-Delta调制器的系统设计,通过比较几种不同结构的调制器性能后,选定单环2阶调制器,并对调制器中非理想因素进行了分析,确定了主要的电路模块。完成了折叠式共源共栅运算放大器、比较器、两相非交叠时钟等子模块设计,确定电路的参数,在Cadence下完成电路的设计和仿真,完成版图设计,并对于版图设计中遇到的问题给予阐述。
采用了0.35μm、N井、2层poly、3层铝线的XFABBCD工艺加以模拟,在电源电压为3.3V,采样速率为32KHZ,过采样比为128倍的条件下,电路仿真结果表明,调制器的信噪比约为80dB,功耗约为330μW ,达到了13bit低功耗∑△ADC调制器的设计指标。
With the rapid development of integrated circuits, the conversion between analog and digital plays a more important role. Among many ADC, Sigma-Delta ADC improves SNR (Signal to Noise Ratio) and reduces the noise in output signal band efficiently by adopting over-sampling and noise-shaping technology. Therefore, the power is reduced. Compared with traditional Nyquist converters, Sigma-Delta ADC decreases the requirements of analogue circuit’s performance specification and device accuracy, simplify the design of analog circuit, and reduce the cost of manufacturing. Currently, there is comparatively high power (>10mW) in high resolution Audio Frequency∑△ADC Converters, this paper design a modulator with 13bit resolution and less than 330μW power consumption based on analysis of the trend of∑△ADC.
This paper analyzes the modulator’s shaping of the quantization noise, discusses several common ADC of Nyquist structure, compares the system design of various Sigma—Delta modulator. After the comparison, 2nd-order modulator has been implemented and non-ideal factors have been analyzed and main circuit blocks have been determined. The design of cascade amplifier, comparator, two-phase non-overlapping clock signal has been finished, parameter of these circuits has been confirmed, the design, simulation and layout design of these circuits under Cadence have been completed. Problems encountered in layout design have also been expatiated.
By adopting the XFAB BCD process with 0.35~μm, N-well, 2P/3M to simulate under the condition of 3.3V power supply, 32kHz sampling rate, 128 oversampling rate, the circuit simulation indicates that the SNR (signal to noise ratio) is about 80db, power consumption is about 330μW , which meets the design specification of 13 bits low power consumption Sigma-Delta ADC modulator.
分析了调制器对量化噪声的整形作用,讨论了几种常见的Nyquist结构的ADC,比较了不同结构的Sigma-Delta调制器的系统设计,通过比较几种不同结构的调制器性能后,选定单环2阶调制器,并对调制器中非理想因素进行了分析,确定了主要的电路模块。完成了折叠式共源共栅运算放大器、比较器、两相非交叠时钟等子模块设计,确定电路的参数,在Cadence下完成电路的设计和仿真,完成版图设计,并对于版图设计中遇到的问题给予阐述。
采用了0.35μm、N井、2层poly、3层铝线的XFABBCD工艺加以模拟,在电源电压为3.3V,采样速率为32KHZ,过采样比为128倍的条件下,电路仿真结果表明,调制器的信噪比约为80dB,功耗约为330μW ,达到了13bit低功耗∑△ADC调制器的设计指标。
With the rapid development of integrated circuits, the conversion between analog and digital plays a more important role. Among many ADC, Sigma-Delta ADC improves SNR (Signal to Noise Ratio) and reduces the noise in output signal band efficiently by adopting over-sampling and noise-shaping technology. Therefore, the power is reduced. Compared with traditional Nyquist converters, Sigma-Delta ADC decreases the requirements of analogue circuit’s performance specification and device accuracy, simplify the design of analog circuit, and reduce the cost of manufacturing. Currently, there is comparatively high power (>10mW) in high resolution Audio Frequency∑△ADC Converters, this paper design a modulator with 13bit resolution and less than 330μW power consumption based on analysis of the trend of∑△ADC.
This paper analyzes the modulator’s shaping of the quantization noise, discusses several common ADC of Nyquist structure, compares the system design of various Sigma—Delta modulator. After the comparison, 2nd-order modulator has been implemented and non-ideal factors have been analyzed and main circuit blocks have been determined. The design of cascade amplifier, comparator, two-phase non-overlapping clock signal has been finished, parameter of these circuits has been confirmed, the design, simulation and layout design of these circuits under Cadence have been completed. Problems encountered in layout design have also been expatiated.
By adopting the XFAB BCD process with 0.35~μm, N-well, 2P/3M to simulate under the condition of 3.3V power supply, 32kHz sampling rate, 128 oversampling rate, the circuit simulation indicates that the SNR (signal to noise ratio) is about 80db, power consumption is about 330μW , which meets the design specification of 13 bits low power consumption Sigma-Delta ADC modulator.
引文
[1]S.R.Norworthy,R.Schreier and G.C.Temes.Detal-sigma Data converters Theory Design and Simulation. IEEE. press: New York.1997.P1-15
[2]Y.Matsuya,K.Uchinura. A 16-bit oversampling A/D conversion technology using triple-integration noise shaping .IEEE .Solid State Circuits. 1987. P921-929.
[3] Ksiser A, Dessouky M. Very low-voltage digital-audio∑△modulator with 88dB dynamic range using local switch bootstrapping. IEEE Solid State Circuit.2001. 349-355
[4]Razavi B.Wooley BA.Design techniques for high-speed,high-resolution comparators IEEE Journal of Solid State Circuits.1992. P1916-1926.
[5]Konihiko lizuka,Hirof-ami Matsul,Masaya Ueda and Mutsuo Daito.A 14-bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary.IEEE Journal of Solid-State Circuits. 2006. P 883-890
[6]B.E.Boser.and.B.A.Wooley..The.Design.of.Sigma-Delta.Modulation.Analog-to- Digital Converters.IEEE Jounral of Solid-State Circuits. l988. P.1298-130.
[7]Yann.Le.Ouillou,Olivier.Gaberieau,Patrice.Gamand,Martin.lsberg,PeterJakobsson, Lars Jonsson,David Le Deaut,Herve Marie,Sven Mattisson,Laurent Monge,TorbjOm Olsson,Sebastien Prouet, and Tobias Tired Highly Integrated Direct Conversion Receiver for GSM/GPRS/EDGE Wilh On-Chip 84-dB Dynamic Range.Continuous-Time.Delta-Sigma.ADC.IEEE.J.solid-State.Circuits.2005.P.403-411.
[8] T.Ritoniemi.T.Karema,H.Tenhunen,and M.Lindell. Fully Differential CMOS Sigma-Delta Modulator for High Performance Analog-to—Digital Conversion with 5VOperating Voltage. IEEE Proceedings of the International Symposium 0n Circuits and Systems. 1988. P2321—2326.
[9] Zhimin Li and Terri S.Fiez.A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 Maz Signal Bandwidth. IEEE.J.solid-State Circuits. 2007. P1873-1882.
[10] W.Chou,P.W.Wong,and R.M.Gray. Multistage Sigms—Delta Modulation. IEEE Transactions on Information Theory. V01.IT-35. 1989. P784-796.
[11]R.W.Stewart and E.Pfann. Oversampling and sigma-delta strategies for data conversion. Electronics & Communication Engineering .1998. P37-47..
[12]Phillip.E.Allen,Douglas.R.Holberg.CMOS.Analog.CircuitDesign.Press:NewYork..Oxford University 002.P123-130.
[13]李向文.一种16位Sigma-Delta音频ADC的设计—调制器模块设计.江南大学硕士学位论文. P10-12
[14]叶英.16bitΣ-△A DC的设计.湖南大学硕士论文. P15-17
[15]C.D.T110mposon and S.R.Bemadas. A Digitally—corrected 20b Delta-Sigma Modulator. ISSCC Digest of Technical Papers.1994. P193-195.
[16]Song Bang-Sup, Lee Seung-Hoon, Tompset Michael F. A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter. IEEE Solid-State Circuits.1990. P1328-1338.
[17]Stephen H Lewis, Gray Paul R. A Pipelined 5-Msample/s 9-bitAnalog-to-Digital Converter. IEEE Solid-State Circuits,. 1987. P954-961.
[18]Behzad Razavi, Wooley Bruce A. A 12-b 5-Msample/s Two-Step CMOS A/D Converter. IEEE Solid-State Circuits. 1992. P1667-1678.
[19]Bossche M vanden, Schoukens J, Renneboeg J. Dynamic Testing and diagnostics of A/D converters. IEEE Transactions on Circuits and System. 1986. P775-785.
[20]朱樟明,杨银堂,孙龙杰等.嵌入式折叠内插式CMOS模数转换器设计.固体电子学研究与进展. P322—326.
[21]克雷伊顿G B.数据转换技术.第1版.杨双林,程朝安,邵慧媛译.北京:北京电子工业出版社.1987. P134-146.
[22]]朱臻,王涛,易婷,何捷等.一种用于高速A/D转换器的全差分、低功耗CMOS运算跨导放大器(OTA).复旦学报. V01.40. NO.1. 2001. P79-85.
[23]李刚模数转换技术及其发展Ⅲ.电子技术应用. 2002. P.72-75.
[24]楼顺天,李博菡.基于MATLAB的系统分析与设计——信号处理.西安::西安电子科技大学出版社. 1998. P15-35.
[25]拉扎维(陈贵灿等译).模拟CMOS集成电路设计西安:西安交通大学出版社. 2003.
[26]张文忠,包兴,姚素英,李树荣,徐江涛.一种低功耗高精度CM0S动态比较器设计与实现.传感技术学报.Mar 2005,18(1),PP.132-135.
[27]李建中,魏同立.一种动态闩锁电压比较嚣的优化设计.电路与系统学报. 2005. P.49-52.
[28]RE.艾伦,DR.霍尔伯格.王正华,叶小琳译. CMOS模拟电路设计.科学出版社. 1995. P20-24.
[29]吴迪. 16位40MHZ过采样Σ△调制器的设计.西北大学硕士学位论文.P9-12.
[30]陈雷.高精度Σ-△ADC的研究.西北工业大学博士学位论文.P8-11.
[2]Y.Matsuya,K.Uchinura. A 16-bit oversampling A/D conversion technology using triple-integration noise shaping .IEEE .Solid State Circuits. 1987. P921-929.
[3] Ksiser A, Dessouky M. Very low-voltage digital-audio∑△modulator with 88dB dynamic range using local switch bootstrapping. IEEE Solid State Circuit.2001. 349-355
[4]Razavi B.Wooley BA.Design techniques for high-speed,high-resolution comparators IEEE Journal of Solid State Circuits.1992. P1916-1926.
[5]Konihiko lizuka,Hirof-ami Matsul,Masaya Ueda and Mutsuo Daito.A 14-bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary.IEEE Journal of Solid-State Circuits. 2006. P 883-890
[6]B.E.Boser.and.B.A.Wooley..The.Design.of.Sigma-Delta.Modulation.Analog-to- Digital Converters.IEEE Jounral of Solid-State Circuits. l988. P.1298-130.
[7]Yann.Le.Ouillou,Olivier.Gaberieau,Patrice.Gamand,Martin.lsberg,PeterJakobsson, Lars Jonsson,David Le Deaut,Herve Marie,Sven Mattisson,Laurent Monge,TorbjOm Olsson,Sebastien Prouet, and Tobias Tired Highly Integrated Direct Conversion Receiver for GSM/GPRS/EDGE Wilh On-Chip 84-dB Dynamic Range.Continuous-Time.Delta-Sigma.ADC.IEEE.J.solid-State.Circuits.2005.P.403-411.
[8] T.Ritoniemi.T.Karema,H.Tenhunen,and M.Lindell. Fully Differential CMOS Sigma-Delta Modulator for High Performance Analog-to—Digital Conversion with 5VOperating Voltage. IEEE Proceedings of the International Symposium 0n Circuits and Systems. 1988. P2321—2326.
[9] Zhimin Li and Terri S.Fiez.A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 Maz Signal Bandwidth. IEEE.J.solid-State Circuits. 2007. P1873-1882.
[10] W.Chou,P.W.Wong,and R.M.Gray. Multistage Sigms—Delta Modulation. IEEE Transactions on Information Theory. V01.IT-35. 1989. P784-796.
[11]R.W.Stewart and E.Pfann. Oversampling and sigma-delta strategies for data conversion. Electronics & Communication Engineering .1998. P37-47..
[12]Phillip.E.Allen,Douglas.R.Holberg.CMOS.Analog.CircuitDesign.Press:NewYork..Oxford University 002.P123-130.
[13]李向文.一种16位Sigma-Delta音频ADC的设计—调制器模块设计.江南大学硕士学位论文. P10-12
[14]叶英.16bitΣ-△A DC的设计.湖南大学硕士论文. P15-17
[15]C.D.T110mposon and S.R.Bemadas. A Digitally—corrected 20b Delta-Sigma Modulator. ISSCC Digest of Technical Papers.1994. P193-195.
[16]Song Bang-Sup, Lee Seung-Hoon, Tompset Michael F. A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter. IEEE Solid-State Circuits.1990. P1328-1338.
[17]Stephen H Lewis, Gray Paul R. A Pipelined 5-Msample/s 9-bitAnalog-to-Digital Converter. IEEE Solid-State Circuits,. 1987. P954-961.
[18]Behzad Razavi, Wooley Bruce A. A 12-b 5-Msample/s Two-Step CMOS A/D Converter. IEEE Solid-State Circuits. 1992. P1667-1678.
[19]Bossche M vanden, Schoukens J, Renneboeg J. Dynamic Testing and diagnostics of A/D converters. IEEE Transactions on Circuits and System. 1986. P775-785.
[20]朱樟明,杨银堂,孙龙杰等.嵌入式折叠内插式CMOS模数转换器设计.固体电子学研究与进展. P322—326.
[21]克雷伊顿G B.数据转换技术.第1版.杨双林,程朝安,邵慧媛译.北京:北京电子工业出版社.1987. P134-146.
[22]]朱臻,王涛,易婷,何捷等.一种用于高速A/D转换器的全差分、低功耗CMOS运算跨导放大器(OTA).复旦学报. V01.40. NO.1. 2001. P79-85.
[23]李刚模数转换技术及其发展Ⅲ.电子技术应用. 2002. P.72-75.
[24]楼顺天,李博菡.基于MATLAB的系统分析与设计——信号处理.西安::西安电子科技大学出版社. 1998. P15-35.
[25]拉扎维(陈贵灿等译).模拟CMOS集成电路设计西安:西安交通大学出版社. 2003.
[26]张文忠,包兴,姚素英,李树荣,徐江涛.一种低功耗高精度CM0S动态比较器设计与实现.传感技术学报.Mar 2005,18(1),PP.132-135.
[27]李建中,魏同立.一种动态闩锁电压比较嚣的优化设计.电路与系统学报. 2005. P.49-52.
[28]RE.艾伦,DR.霍尔伯格.王正华,叶小琳译. CMOS模拟电路设计.科学出版社. 1995. P20-24.
[29]吴迪. 16位40MHZ过采样Σ△调制器的设计.西北大学硕士学位论文.P9-12.
[30]陈雷.高精度Σ-△ADC的研究.西北工业大学博士学位论文.P8-11.