片上网络通讯结构可测性设计
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摘要
测试已经成了集成电路设计制造中不可分割的一部分,而且随着集成电路工艺复杂度和设计复杂度的提高,集成电路的测试变得越来越困难,也变得越来越重要。在这种情况下,可测性设计(Design For Test)技术成为解决芯片生产测试问题的主要手段之一,日益引起人们的重视。片上网络(NoC)结构的显著特点是规模巨大和互连通讯复杂。如此大规模的结构其制造故障也会随之提高,这就对其测试提出了更高程度的要求,需要采用合理的测试策略及测试体系来对片上网络进行测试,以节省测试开销。因此研究NoC测试策略及测试体系对解决NoC及未来电路测试难点有重要意义。
本文首先阐述了测试的基本概念,简单地描述了故障检测的基本原理以及现有的一些可测性方法。
NoC通讯结构的测试分为两部分:路由开关间互连线的测试和路由开关的测试。针对路由开关间互连线的测试,采用MAF测试模型,利用BIST测试法,设计了TDG单元和TED单元,并通过软件进行了仿真和综合。对于路由开关的测试,由于NoC中数据是以报文的方式进行传播,则可以把测试数据封装成报文的形式,通过路由开关在通讯网络中传播,进而对路由开关进行测试。根据报文地址段的不同,测试可以分为两种:单播测试法和多播测试法。最后分析了两种方法的测试时间。
然后本文针对NoC中资源网络接口的多时钟域问题,设计了异步FIFO,利用软件对其进行功能仿真。并通过插入扫描链和隔离双端口存储器,设计了异步FIFO的测试结构。仿真结果显示,插入扫描链后电路的面积和功耗有少量增加。最后本文对NoC测试技术的未来发展方向进行了展望。
Testing is a necessary part of the IC design process. Due to the continuous increase in the complexity of IC design and process, design for test(DFT) technology is being more and more diffcult as well as important. And system-on-chip(SoC), which embraced various reused IP cores, makes the testing even more prominent. Now the chip design has developed SoC into NoC which is the communicating of multiple SoC. There are large number of transistors and more complex functions in a single chip. In addition under the pressure of market, we must decrease the design period and use a mass of IP cores in design. So NoC architecture has characteristics of large scale and complexity of communication. But the faults during manufacturing become more difficult to test in large scale architecture.We must research advanced test measure, that is using feasible measure and structure in the testing of NoC to reduce the cost of testing. Thus it is significant to research the test measure and the structure of NoC and even future circuits.
In this paper, the conception of DFT is displayed firstly and some conventional test methods are showed.
The test of NoC communication structure is divided into two parts: the test of inter-switch links, and test of switchs. We use the MAF model and BIST method to test the inter-switch links. The TDG unit and TED unit are designed, simulated and synthesized in this paper. Because datas are transmitted in the form of packets, we can test the switchs with the test packets composed of test datas. This paper proposes two different strategies for implementing the test: sequential test strategy and multicast test strategy. Then we analyze the test time of two strategys.
A kind of two clocks asynchronous FIFO is designed, which is used to resolve the metastability with communication between different clock regions. This paper insets a scan chain and isolates the dual ports memory, and designs the test structure. The result shows that the area and power of the circuit exhibits a little increase.
Finally, the paper looks forward to the NoC test technology.
本文首先阐述了测试的基本概念,简单地描述了故障检测的基本原理以及现有的一些可测性方法。
NoC通讯结构的测试分为两部分:路由开关间互连线的测试和路由开关的测试。针对路由开关间互连线的测试,采用MAF测试模型,利用BIST测试法,设计了TDG单元和TED单元,并通过软件进行了仿真和综合。对于路由开关的测试,由于NoC中数据是以报文的方式进行传播,则可以把测试数据封装成报文的形式,通过路由开关在通讯网络中传播,进而对路由开关进行测试。根据报文地址段的不同,测试可以分为两种:单播测试法和多播测试法。最后分析了两种方法的测试时间。
然后本文针对NoC中资源网络接口的多时钟域问题,设计了异步FIFO,利用软件对其进行功能仿真。并通过插入扫描链和隔离双端口存储器,设计了异步FIFO的测试结构。仿真结果显示,插入扫描链后电路的面积和功耗有少量增加。最后本文对NoC测试技术的未来发展方向进行了展望。
Testing is a necessary part of the IC design process. Due to the continuous increase in the complexity of IC design and process, design for test(DFT) technology is being more and more diffcult as well as important. And system-on-chip(SoC), which embraced various reused IP cores, makes the testing even more prominent. Now the chip design has developed SoC into NoC which is the communicating of multiple SoC. There are large number of transistors and more complex functions in a single chip. In addition under the pressure of market, we must decrease the design period and use a mass of IP cores in design. So NoC architecture has characteristics of large scale and complexity of communication. But the faults during manufacturing become more difficult to test in large scale architecture.We must research advanced test measure, that is using feasible measure and structure in the testing of NoC to reduce the cost of testing. Thus it is significant to research the test measure and the structure of NoC and even future circuits.
In this paper, the conception of DFT is displayed firstly and some conventional test methods are showed.
The test of NoC communication structure is divided into two parts: the test of inter-switch links, and test of switchs. We use the MAF model and BIST method to test the inter-switch links. The TDG unit and TED unit are designed, simulated and synthesized in this paper. Because datas are transmitted in the form of packets, we can test the switchs with the test packets composed of test datas. This paper proposes two different strategies for implementing the test: sequential test strategy and multicast test strategy. Then we analyze the test time of two strategys.
A kind of two clocks asynchronous FIFO is designed, which is used to resolve the metastability with communication between different clock regions. This paper insets a scan chain and isolates the dual ports memory, and designs the test structure. The result shows that the area and power of the circuit exhibits a little increase.
Finally, the paper looks forward to the NoC test technology.
引文
[1] Alfred L. Crouch, Design-for-Test for Digital IC’s and Embedded Core system, USA: Prentice Hall PRT. 1999
[2] G. R. Case, Analysis of Actual Fault Mechanisms in CMOS Logic Gates, Proc. Of 13th Design Automation Conf,. June 1976, pp. 265-270.
[3] J. Partridge, Testing for Bipolar Integrated Circuit Failure Modes, Digest of Papers 1980 Test Conf,. November 1980, pp. 397-406.
[4] J. P. Shen, W. Maly, and F. J. Ferguson, Inductive Fault Analysis of MOS Integrated Circuits, IEEE Design & Test of Computers, December 1985, Vol. 2, No. 6, pp. 13-26.
[5] C. Timoc, M. Buehler, T. Griswold, C. Pina, F. Scott, and L. Hess, Logical Models of Physical Failures, Proc. of International Test Conf,. October 1983, pp. 546-553.
[6] H.-K. T. Ma, S. Devadas, A. Sangiovanni-Vincentelli, and R. Wei, Logic Verification Algorithms and their Parallel Implementation, IEEE Trans. On Computer-Aided Design, Feb. 1989, Vol. 8, No. 2, pp. 181-189.
[7] J. P. Roth, Diagnosis of Automata Failures: A Calculus and a Method, IBM Journal of Research and Development, July 1966, Vol. 10, No. 4, pp. 278-291.
[8] P. Goel, An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits, IEEE Transactions on Computers, Vol. C-30, No.3, pp. 215-222,1981.
[9] H. Fujiwara and T. Shimono, On the Acceleration of Test Pattern Algorithms, IEEE Transactions on Computers, Vol. C-32, No. 12, 1983, pp. 1137-1144.
[10] H. K. Lee and D. S. Ha, Atalanta: an Efficient ATPG for Combinational Circuits, Technical Report, 93-12, Dep’t of Electrical Eng., Virginia Polyte chnic Institute and State University, Blacksburg, Virginiam, 1993.
[11] I. Hamzaoglu and J. H. Patel, Test Set Compaction Algorithms for Combinational Circuits, In proceedings of IEEE International Conference on Computer-Aided Design, November, 1998.
[12] I. Hamzaoglu, J. H. Patel, New Techniques for Deterministic Test Pattern Generation, In proceedings of IEEE VLSI Test Symposium, April 1998,pp.446-452.
[13] A. M. Rincon, C. Cherichetti, J. A. Monzel, D. R. Stauffer, and M. T. Trick, CoreDesign and Systen-on-a-chip Integration, IEEE Design & Test of Computers, vol. 14, Dec. 1997, pp. 26-35.
[14] Miron Abranmovici, Melvin A. Breuer, Arthur D. Friedman. Digital Systems Testing and Testable Design,清华大学出版社影印。
[15] IEEE Standard for a Mixed-Signal Test Bus. Approved 26 June 1999, IEEE-SA Standards Board. IEEE Std1149.4-1999.
[16] Kenneth P. Parker. The Boundary-Scan Handbook (third). Kluwer Academic Publishers. 2003.
[17] IEEE Standard Testability Method for Embedded Core-based Integrated Circuits.
[18] Y. Zorian, Test Requirements for Embedded Core-Based Systems and IEEE P1500, in Proceedings IEEE International Test Conference(ITC), IEEE Computer SoCiety Press, Nov. 1997, pp.191-199.
[19] E. J. Marinissen, R. Kapur, and Y. Zorian, On Using IEEE P1500 SECT for Test Plug-n-Play, in Proceedings IEEE International Test Conference(ITC), IEEE Computer SoCiety Press, Oct. 2000, pp. 770-777.
[20] R. Kapur, M. Lousberg, T. Taylor, B. Keller, P. Reuter, and D. Kay, CTL, The Language for Describing Core-based Test, in Proceedings IEEE Inter national Test Conference(ITC), IEEE Computer SoCiety Press, Oct. 2001.
[21] E. J. Marinissen, S. K. Goel, and M. Lousberg, Wrapper Design for Embedded Core Test, in Proceedings IEEE International Test Conference(ITC), IEEE Computer Society Press, Oct. 2000.
[22] Vishwani D. Agrawal, CharlesR. Kime and Kewal. A Tutorial on Built-In Self-Test (Part 2: Applications) [J], IEEE Design& Test of Computer, 1993, (6), pp. 69 -77.
[23] A lfredL .Crouch.数字集成电路与嵌入式内核系统可测试性设计,中国电力出版社,2004.
[24] C HARLES等。数字系统的内装自测试,计算机与数字工程,No. 2,1996.
[25] L. Benini and D. Bertozzi. Network-on-chip architectures and design methods. IEE Proc.–Comput. DigitTech., Vol.152, No.2,March 2005. 261-272.
[26]高明伦,杜高明。NoC:下一代集成电路主流设计技术,微电子学,Aug. 2006.
[27]姜鹏。基于NoC体系结构的测试研究,西北工业大学,Mar. 2005.
[28] P Guerrier, A Greiner. A Generic Architecture for on-chip packet-switched Interconnections.In Proceedings of Design, Automation and test in Europe, 2000: 250-255.
[29] Axel Jantsch等. Networks on Chip, Kluwer Academic Publishers, 2003.
[30] E. Cota, Luigi Caro, Flavio Wagner, et al.Power aware NoC Reuse on the Testingof Core-Based Systems.Proceedings of ITC 2003, pp.612-621.
[31] Cristian, Grecu et al. BIST for Network-on-Chip Interconnect Infrast- ructures. Proceedings of the 24th IEEE VLSI Test Symposium. 2006.
[32] M.Cuviello, S. Dey,X. Bai, Y. Zhao,“Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects”,Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, Nov.1999, pp. 297-303.
[33] T. Mudge.“Power: A First-Class Architectural Design Constraint”, IEEE Computer,20 01,34 (1).
[34] Cristian Crecu, Partha Pande,etc. Method Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05). 2005.
[35] Crews. M, Yong. Y. Practical Design for Transferring Signals Between Clock Domains. EDN, 2002, 48(4): pp.65.
[36] Ran Ginosar. Fourteen Ways to Fool Your Synchronizer. Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on, 12-15 May 2003, Pages: 89-96.
[37] Cliford E. Cummings, "Synthesis and Scripting Techniques forDe signing Multi-AsynchronousC lockD esigns,"S NUG2001了SynopsysUs ers G roupC onference,S anJ ose,C A,2 009)U serP apers,M arch2 001,Se ction MC1, 3rd paper. Also available at www.sunburst-design.com/papers.
[38] Injong Rhee. Optimizing a FIFO, Scalable Spin Lock Using Consistent Memory. Real-Time Systems Symposium, 1996. 17th IEEE, 4-6Dec.1996 Pages: 106-114.
[39] Cliford E. Cummings. Simulation and Synthesis Techniques for Asynchronous FIFO Design. SNUG San Jose 2002 Simulation and Synthesis Techniques for Rev1.1.
[40] V. Agrawal, K.-T. Cheng, D. Johnson, and T. Lin. Designing Circuits with Partial Scan. IEEE Design & Test of Computers, 5:8-15, April 1988.
[41] Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Partial-scan delay fault testing of asynchronous circuits Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 17, Issue 11, Nov. 1998 Page(s):1184– 1199.
[2] G. R. Case, Analysis of Actual Fault Mechanisms in CMOS Logic Gates, Proc. Of 13th Design Automation Conf,. June 1976, pp. 265-270.
[3] J. Partridge, Testing for Bipolar Integrated Circuit Failure Modes, Digest of Papers 1980 Test Conf,. November 1980, pp. 397-406.
[4] J. P. Shen, W. Maly, and F. J. Ferguson, Inductive Fault Analysis of MOS Integrated Circuits, IEEE Design & Test of Computers, December 1985, Vol. 2, No. 6, pp. 13-26.
[5] C. Timoc, M. Buehler, T. Griswold, C. Pina, F. Scott, and L. Hess, Logical Models of Physical Failures, Proc. of International Test Conf,. October 1983, pp. 546-553.
[6] H.-K. T. Ma, S. Devadas, A. Sangiovanni-Vincentelli, and R. Wei, Logic Verification Algorithms and their Parallel Implementation, IEEE Trans. On Computer-Aided Design, Feb. 1989, Vol. 8, No. 2, pp. 181-189.
[7] J. P. Roth, Diagnosis of Automata Failures: A Calculus and a Method, IBM Journal of Research and Development, July 1966, Vol. 10, No. 4, pp. 278-291.
[8] P. Goel, An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits, IEEE Transactions on Computers, Vol. C-30, No.3, pp. 215-222,1981.
[9] H. Fujiwara and T. Shimono, On the Acceleration of Test Pattern Algorithms, IEEE Transactions on Computers, Vol. C-32, No. 12, 1983, pp. 1137-1144.
[10] H. K. Lee and D. S. Ha, Atalanta: an Efficient ATPG for Combinational Circuits, Technical Report, 93-12, Dep’t of Electrical Eng., Virginia Polyte chnic Institute and State University, Blacksburg, Virginiam, 1993.
[11] I. Hamzaoglu and J. H. Patel, Test Set Compaction Algorithms for Combinational Circuits, In proceedings of IEEE International Conference on Computer-Aided Design, November, 1998.
[12] I. Hamzaoglu, J. H. Patel, New Techniques for Deterministic Test Pattern Generation, In proceedings of IEEE VLSI Test Symposium, April 1998,pp.446-452.
[13] A. M. Rincon, C. Cherichetti, J. A. Monzel, D. R. Stauffer, and M. T. Trick, CoreDesign and Systen-on-a-chip Integration, IEEE Design & Test of Computers, vol. 14, Dec. 1997, pp. 26-35.
[14] Miron Abranmovici, Melvin A. Breuer, Arthur D. Friedman. Digital Systems Testing and Testable Design,清华大学出版社影印。
[15] IEEE Standard for a Mixed-Signal Test Bus. Approved 26 June 1999, IEEE-SA Standards Board. IEEE Std1149.4-1999.
[16] Kenneth P. Parker. The Boundary-Scan Handbook (third). Kluwer Academic Publishers. 2003.
[17] IEEE Standard Testability Method for Embedded Core-based Integrated Circuits.
[18] Y. Zorian, Test Requirements for Embedded Core-Based Systems and IEEE P1500, in Proceedings IEEE International Test Conference(ITC), IEEE Computer SoCiety Press, Nov. 1997, pp.191-199.
[19] E. J. Marinissen, R. Kapur, and Y. Zorian, On Using IEEE P1500 SECT for Test Plug-n-Play, in Proceedings IEEE International Test Conference(ITC), IEEE Computer SoCiety Press, Oct. 2000, pp. 770-777.
[20] R. Kapur, M. Lousberg, T. Taylor, B. Keller, P. Reuter, and D. Kay, CTL, The Language for Describing Core-based Test, in Proceedings IEEE Inter national Test Conference(ITC), IEEE Computer SoCiety Press, Oct. 2001.
[21] E. J. Marinissen, S. K. Goel, and M. Lousberg, Wrapper Design for Embedded Core Test, in Proceedings IEEE International Test Conference(ITC), IEEE Computer Society Press, Oct. 2000.
[22] Vishwani D. Agrawal, CharlesR. Kime and Kewal. A Tutorial on Built-In Self-Test (Part 2: Applications) [J], IEEE Design& Test of Computer, 1993, (6), pp. 69 -77.
[23] A lfredL .Crouch.数字集成电路与嵌入式内核系统可测试性设计,中国电力出版社,2004.
[24] C HARLES等。数字系统的内装自测试,计算机与数字工程,No. 2,1996.
[25] L. Benini and D. Bertozzi. Network-on-chip architectures and design methods. IEE Proc.–Comput. DigitTech., Vol.152, No.2,March 2005. 261-272.
[26]高明伦,杜高明。NoC:下一代集成电路主流设计技术,微电子学,Aug. 2006.
[27]姜鹏。基于NoC体系结构的测试研究,西北工业大学,Mar. 2005.
[28] P Guerrier, A Greiner. A Generic Architecture for on-chip packet-switched Interconnections.In Proceedings of Design, Automation and test in Europe, 2000: 250-255.
[29] Axel Jantsch等. Networks on Chip, Kluwer Academic Publishers, 2003.
[30] E. Cota, Luigi Caro, Flavio Wagner, et al.Power aware NoC Reuse on the Testingof Core-Based Systems.Proceedings of ITC 2003, pp.612-621.
[31] Cristian, Grecu et al. BIST for Network-on-Chip Interconnect Infrast- ructures. Proceedings of the 24th IEEE VLSI Test Symposium. 2006.
[32] M.Cuviello, S. Dey,X. Bai, Y. Zhao,“Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects”,Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, Nov.1999, pp. 297-303.
[33] T. Mudge.“Power: A First-Class Architectural Design Constraint”, IEEE Computer,20 01,34 (1).
[34] Cristian Crecu, Partha Pande,etc. Method Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05). 2005.
[35] Crews. M, Yong. Y. Practical Design for Transferring Signals Between Clock Domains. EDN, 2002, 48(4): pp.65.
[36] Ran Ginosar. Fourteen Ways to Fool Your Synchronizer. Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on, 12-15 May 2003, Pages: 89-96.
[37] Cliford E. Cummings, "Synthesis and Scripting Techniques forDe signing Multi-AsynchronousC lockD esigns,"S NUG2001了SynopsysUs ers G roupC onference,S anJ ose,C A,2 009)U serP apers,M arch2 001,Se ction MC1, 3rd paper. Also available at www.sunburst-design.com/papers.
[38] Injong Rhee. Optimizing a FIFO, Scalable Spin Lock Using Consistent Memory. Real-Time Systems Symposium, 1996. 17th IEEE, 4-6Dec.1996 Pages: 106-114.
[39] Cliford E. Cummings. Simulation and Synthesis Techniques for Asynchronous FIFO Design. SNUG San Jose 2002 Simulation and Synthesis Techniques for Rev1.1.
[40] V. Agrawal, K.-T. Cheng, D. Johnson, and T. Lin. Designing Circuits with Partial Scan. IEEE Design & Test of Computers, 5:8-15, April 1988.
[41] Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Partial-scan delay fault testing of asynchronous circuits Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 17, Issue 11, Nov. 1998 Page(s):1184– 1199.