基于FPGA的可靠性设计
|
摘要
设备的可靠性是衡量系统安全的重要指标。随着电子技术的不断发展,FPGA器件深入应用到军队、航天、地面交通等领域,FPGA能够进行重复编程,便于修改,安全性强,适用于硬件设备的开发。与此同时,广泛的应用也对其可靠性提出巨大挑战。本论文基于实验室承担的铁道部高速列控系统中应答器传输模块(BTM)的研制任务,针对其中出现的“丢点”问题,进行一系列的可靠性的研究,总结了提高FPGA以及设备可靠性的关键设计。本论文研究成果如下：
1、利用FPGA速度和面积互换的原则,考虑整个工程稳定运行能够达到的最高时钟频率与FPGA内部各个寄存器的时间关系以及FPGA与外部器件接口的各种时序要求,提出了针对跨时钟领域的安全通信以高速信号处理方法并进行仿真验证,从而得到了FPGA片内的可靠性设计方案；
2、在研究了芯片内部可靠性的基础之上,结合BTM的特点,提出一种分布式的带有高速数据传输总线的异步收发机,旨在提高BTM的抗风险性。运用马尔科夫模型建立了系统状态转移图,研究了故障率、维修率、故障检测覆盖率等参数对系统的安全性、可靠性的影响,在此基础上进行异步收发机的交互通信设计以及设备的故障-安全设计；
3、最后对整个系统进行实际验证,考察其可靠性。验证结果表明,本课题设计的分布式二乘二取二异步收发机有很高的可靠性和可行性。
我国铁路需要高性能的列车运行控制系统为高速列车的安全提供有力保障。本研究课题正是从此角度出发,进行设备可靠性的设计,并且具有低功耗,便于升级,安全可靠的特点。已经在高铁京沪线上通过铁道部的鉴定,具有广阔的应用和发展空间。
The reliability of equipments is an important indicator to measure the system security. With the continuous development of electronic technology, FPGA devices is deeply applied to the military, aerospace, ground transportation and other fields, FPGA can be reprogrammed, easy to modify, have a strong security, and suitable for hardware development. At the same time, the extensive using of FPGA is also an enormous challenge to its reliability. This paper based on a lab's project of BTM research and development, which is a part of high-speed train control system of the Ministry of Railways. For the "lost point" problem in BTM project, a series of research of reliability and a summarize of improving the FPGAs and equipments'reliability have been done in this paper. The main achievements are as follows.
1、Using the principle of speed and area exchange and considering the timing relationships between the whole system reliability and internal registers, and the external I/O interface timing requirements, this paper gives a design and simulation of safe telecommunication for crossing clock and a design and simulation for high-speed signal processing, gets a chip design of FPGA reliability.
2. On the basis of chip reliability, this paper gives an asynchronous data transmission bus with characteristics of distributed and high-speed to increase the anti-risk of BTM. The system status switching graph is created using Markov models. The influence of parameters as failure rate, maintenance rate and failure usability on the system security, reliability, and availability is studied. On the basis this paper designs the interaction asynchronous communication transceiver with failure-security design.
3. At last this paper makes actual verification of the entire system to research its reliability. The result shows that the distributed Double 2-vote-2 asynchronous transceiver has a high reliability and feasibility.
China's railway train requires high-performance high-speed train control system to provide strong security protection. The research design of reliability equipment from this point, which has characteristics of low power consumption, easy upgrade, safe and reliable. The project has been identification by the Ministry of Railways in Beijing-Shanghai high speed rail line, has broad application space.
1、利用FPGA速度和面积互换的原则,考虑整个工程稳定运行能够达到的最高时钟频率与FPGA内部各个寄存器的时间关系以及FPGA与外部器件接口的各种时序要求,提出了针对跨时钟领域的安全通信以高速信号处理方法并进行仿真验证,从而得到了FPGA片内的可靠性设计方案；
2、在研究了芯片内部可靠性的基础之上,结合BTM的特点,提出一种分布式的带有高速数据传输总线的异步收发机,旨在提高BTM的抗风险性。运用马尔科夫模型建立了系统状态转移图,研究了故障率、维修率、故障检测覆盖率等参数对系统的安全性、可靠性的影响,在此基础上进行异步收发机的交互通信设计以及设备的故障-安全设计；
3、最后对整个系统进行实际验证,考察其可靠性。验证结果表明,本课题设计的分布式二乘二取二异步收发机有很高的可靠性和可行性。
我国铁路需要高性能的列车运行控制系统为高速列车的安全提供有力保障。本研究课题正是从此角度出发,进行设备可靠性的设计,并且具有低功耗,便于升级,安全可靠的特点。已经在高铁京沪线上通过铁道部的鉴定,具有广阔的应用和发展空间。
The reliability of equipments is an important indicator to measure the system security. With the continuous development of electronic technology, FPGA devices is deeply applied to the military, aerospace, ground transportation and other fields, FPGA can be reprogrammed, easy to modify, have a strong security, and suitable for hardware development. At the same time, the extensive using of FPGA is also an enormous challenge to its reliability. This paper based on a lab's project of BTM research and development, which is a part of high-speed train control system of the Ministry of Railways. For the "lost point" problem in BTM project, a series of research of reliability and a summarize of improving the FPGAs and equipments'reliability have been done in this paper. The main achievements are as follows.
1、Using the principle of speed and area exchange and considering the timing relationships between the whole system reliability and internal registers, and the external I/O interface timing requirements, this paper gives a design and simulation of safe telecommunication for crossing clock and a design and simulation for high-speed signal processing, gets a chip design of FPGA reliability.
2. On the basis of chip reliability, this paper gives an asynchronous data transmission bus with characteristics of distributed and high-speed to increase the anti-risk of BTM. The system status switching graph is created using Markov models. The influence of parameters as failure rate, maintenance rate and failure usability on the system security, reliability, and availability is studied. On the basis this paper designs the interaction asynchronous communication transceiver with failure-security design.
3. At last this paper makes actual verification of the entire system to research its reliability. The result shows that the distributed Double 2-vote-2 asynchronous transceiver has a high reliability and feasibility.
China's railway train requires high-performance high-speed train control system to provide strong security protection. The research design of reliability equipment from this point, which has characteristics of low power consumption, easy upgrade, safe and reliable. The project has been identification by the Ministry of Railways in Beijing-Shanghai high speed rail line, has broad application space.
引文
[1]夏宇闻Verilog数字系统设计教程 第2版 北京航空航天大学出版社2008 10-312
[2]佟立本 铁道概论 中国铁道出版社第4版 1999 142-155
[3]吴汶麟 国外铁路信号新技术 中国铁道出版社2000 61-120
[4]刘延飞,郭锁利,王晓戎 基于Altera FPGA/CPLD的电子系统设计及工程实践人民邮电出版社2009
[5]罗苑棠CPLD/FPGA常用模块与综合系统设计 电子工业出版社2007
[6]刘睿强FPGA应用技术及实践北京理工大学出版社2011 142-143
[7]曹杰 二乘二取二计算机连锁控制系统的研究[学位论文],天津,天津大学,2009
[8]ALTERA Metastability in Altera Devices ALTERA ver.4 1999
[9]李亚伯 数字电路逻辑设计 第4版 大连理工大学出版社 2005156-160
[10]马金明,吕铁军,杨紫珊 数字系统与逻辑设计北京航空航天大学出版社2007 124-134
[11]蔡敏 基于容错技术的温湿度数据采集系统 [学位论文],天津,天津大学,2009
[12]廖丽君 高速列车运行控制系统仿真[学位论文],北京,北京交通大学,2009
[13]孙蕾 二乘二取二计算机连锁系统的设计与实现 [学位论文],北京,北京交通大学,2005
[14]高宏 基于通用计算机的二取二安全计算平台的研究 [学位论文],北京,北京交通大学,2009
[15]宋沛东 CTCS3级列控系统仿真测试平台——无线闭塞中心仿真子系统的研究[学位论文],北京,北京交通大学,2007
[16]黄良,韩诚山,文明 星载FPGA混合时钟域设计 电子技术应用 第36卷,第12期2010
[17]唐辉艳,李绍胜FPGA设计中跨时钟域同步方法的研究铁路计算机应用Vol.41,No.2 2011
[18]肖静娴 基于FPGA的异步FIFO缓存设计 电子测量技术第32卷,第11期2009
[19]祝异翔 基于Verilog HDL的IS-95 CDMA反向接入信道模块的研究[学位 论文],天津,天津大学,2004
[20]杨宏亮,金炎胜,王刚毅FPGA设计中状态机安全性研究 黑龙江科学Vol.2,No.2 2011
[21]吴厚航 深入浅出玩转FPGA北京航空航天大学出版社2010
[22]Managing metastability with the QuartusⅡ Software-tera QuartusⅡ Handbook Versionll.1.0 Volume 1 2011
[23]黄隶凡,郑学仁FPGA设计中的亚稳态研究微电子学Vol.41,No.2 2682011
[24]易志明,林凌,郝丽宏 SPI串行总线接口及其实现 自动化与仪器仪表104期2002
[25]李翔 基于FPGA的二乘二取二安全系统的设计与实现 [学位论文],北京,北京交通大学20092
[26]刘韬,楼兴华FPGA数字电子系统设计与开发实例导航人民邮电出版社2005 127-172
[27]徐宁,张季良,王财进 列车高速运行条件下应答器车载测试设备关键技术中国铁道科学Vol.31 No.4 2010
[28]Hyunki Kim,Hyeunate Lee,Keyseo Lee The design and analysis of AVTMR (all voting triple modular redundancy) and dual-duplex system Reliability Engineering and System Safety(S0951-8320),2005,88(3):291-300
[29]张本宏 “二乘二取二”冗余系统的可靠性和安全性分析 系统仿真学报Vol21,No.1 2009
[30]莫艾JTAG边界扫描在FPGA中的应用及电路设计[学位论文],西安,西安电子科技大学,2008
[31]姚远,韦宏卫FPGA应用开发入门与典型实例 人民邮电出版社2008162-163
[32]曾洁毅,赵会兵 应答器传输模块测试的研究北京交通大学学报Vol.32,No.2 2008
[2]佟立本 铁道概论 中国铁道出版社第4版 1999 142-155
[3]吴汶麟 国外铁路信号新技术 中国铁道出版社2000 61-120
[4]刘延飞,郭锁利,王晓戎 基于Altera FPGA/CPLD的电子系统设计及工程实践人民邮电出版社2009
[5]罗苑棠CPLD/FPGA常用模块与综合系统设计 电子工业出版社2007
[6]刘睿强FPGA应用技术及实践北京理工大学出版社2011 142-143
[7]曹杰 二乘二取二计算机连锁控制系统的研究[学位论文],天津,天津大学,2009
[8]ALTERA Metastability in Altera Devices ALTERA ver.4 1999
[9]李亚伯 数字电路逻辑设计 第4版 大连理工大学出版社 2005156-160
[10]马金明,吕铁军,杨紫珊 数字系统与逻辑设计北京航空航天大学出版社2007 124-134
[11]蔡敏 基于容错技术的温湿度数据采集系统 [学位论文],天津,天津大学,2009
[12]廖丽君 高速列车运行控制系统仿真[学位论文],北京,北京交通大学,2009
[13]孙蕾 二乘二取二计算机连锁系统的设计与实现 [学位论文],北京,北京交通大学,2005
[14]高宏 基于通用计算机的二取二安全计算平台的研究 [学位论文],北京,北京交通大学,2009
[15]宋沛东 CTCS3级列控系统仿真测试平台——无线闭塞中心仿真子系统的研究[学位论文],北京,北京交通大学,2007
[16]黄良,韩诚山,文明 星载FPGA混合时钟域设计 电子技术应用 第36卷,第12期2010
[17]唐辉艳,李绍胜FPGA设计中跨时钟域同步方法的研究铁路计算机应用Vol.41,No.2 2011
[18]肖静娴 基于FPGA的异步FIFO缓存设计 电子测量技术第32卷,第11期2009
[19]祝异翔 基于Verilog HDL的IS-95 CDMA反向接入信道模块的研究[学位 论文],天津,天津大学,2004
[20]杨宏亮,金炎胜,王刚毅FPGA设计中状态机安全性研究 黑龙江科学Vol.2,No.2 2011
[21]吴厚航 深入浅出玩转FPGA北京航空航天大学出版社2010
[22]Managing metastability with the QuartusⅡ Software-tera QuartusⅡ Handbook Versionll.1.0 Volume 1 2011
[23]黄隶凡,郑学仁FPGA设计中的亚稳态研究微电子学Vol.41,No.2 2682011
[24]易志明,林凌,郝丽宏 SPI串行总线接口及其实现 自动化与仪器仪表104期2002
[25]李翔 基于FPGA的二乘二取二安全系统的设计与实现 [学位论文],北京,北京交通大学20092
[26]刘韬,楼兴华FPGA数字电子系统设计与开发实例导航人民邮电出版社2005 127-172
[27]徐宁,张季良,王财进 列车高速运行条件下应答器车载测试设备关键技术中国铁道科学Vol.31 No.4 2010
[28]Hyunki Kim,Hyeunate Lee,Keyseo Lee The design and analysis of AVTMR (all voting triple modular redundancy) and dual-duplex system Reliability Engineering and System Safety(S0951-8320),2005,88(3):291-300
[29]张本宏 “二乘二取二”冗余系统的可靠性和安全性分析 系统仿真学报Vol21,No.1 2009
[30]莫艾JTAG边界扫描在FPGA中的应用及电路设计[学位论文],西安,西安电子科技大学,2008
[31]姚远,韦宏卫FPGA应用开发入门与典型实例 人民邮电出版社2008162-163
[32]曾洁毅,赵会兵 应答器传输模块测试的研究北京交通大学学报Vol.32,No.2 2008