高性能路由器故障测试技术研究与实现
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摘要
高性能路由器在新一代高速IP网络中发挥着巨大的作用，其规模越来越大，路由器的可靠性要求随之变得越来越高。实现高可靠性路由器系统的技术途径从根本上说有两条：一条是避错，一条是容错，都需要进行故障检测与诊断技术的研究。
随着微电子技术的飞速发展，越来越多的超大规模电路应用于路由器系统，导致系统的复杂性急剧提高，使常规的故障诊断技术和可靠性设计变得十分复杂和困难。
本文以863“下一代互联网实验环境”为课题背景，针对高性能路由器的硬件体系结构，详细研究分析了路由器系统中的故障形式，建立了相应的故障模型，并着重进行了故障模型的化简。在详细分析了常见故障模型的特点后，对它们的共同特征进行了抽象，并在此基础上，提出了一种新颖的类PLA结构模型。该模型包括输入输出以及连接两者的传输线，通过线与线之间的接合模拟了在数据传输过程中可能出现的故障。通过合理的论证，我们将故障形式在此模型上进行了有效的规整和缩减。
其次，在类PLA故障模型的基础上，我们对故障测试算法进行了详细的研究，对系统单故障和多故障的检测给出了必要的证明，并以此作为依据，产生出路由器系统常见故障的完全测试集，同时给出了故障测试算法的流程。
最后，我们在两个国家863重点任务中，以类PLA模型为指导，设计并实现了基于专用转发引擎和基于网络处理器的路由器硬件测试诊断系统。
High-performance network routers play an important role in the next generation high-speed IP network, their scales become larger and larger. Therefore, we need higher and higher reliability for router system. The technological approaches have only two: one is fault avoidance; and one is fault tolerance. The research for fault check and fault diagnosis must be taken into account to realize these two approaches.
Along with rapid development of micro-electronics technology, more and more Very Large Scale Integrate circuits are applied into router system, and this makes system more complex, and makes traditional fault diagnosis and reliability design more complex and more difficult.
The background for this research is "Experimental environment for Next Generation Internet" of 863. Aiming at the hardware architecture of high performance router system, we analyze and study the fault forms in router system carefully and set up relevant fault models for these forms, and we take fault models reduction into account. After analyzing the characteristics of all familiar faults carefully, we get their common characteristic and present one novel fault model which is analogous to PLA architecture. It comprise input line and output line and transfer line which connect input and output. This model simulate those likely faults which emerge in transfer process through connection of lines. Through reasonable hypothesis and demonstration, fault forms are standardized and reduced effectively on this model.
Based analogous PLA model, we make careful research on the algorithm of fault test, and present the relevant proof for single fault and multiple faults check of system. Then we come into being complete test set for familiar faults of router system and present the flow about this algorithm.
At last, we apply this algorithm into two significant tasks of 863. Based analogous PLA model, we design and implement two hardware test and diagnosis systems for router system based special forward engine and router system based network processor.
随着微电子技术的飞速发展，越来越多的超大规模电路应用于路由器系统，导致系统的复杂性急剧提高，使常规的故障诊断技术和可靠性设计变得十分复杂和困难。
本文以863“下一代互联网实验环境”为课题背景，针对高性能路由器的硬件体系结构，详细研究分析了路由器系统中的故障形式，建立了相应的故障模型，并着重进行了故障模型的化简。在详细分析了常见故障模型的特点后，对它们的共同特征进行了抽象，并在此基础上，提出了一种新颖的类PLA结构模型。该模型包括输入输出以及连接两者的传输线，通过线与线之间的接合模拟了在数据传输过程中可能出现的故障。通过合理的论证，我们将故障形式在此模型上进行了有效的规整和缩减。
其次，在类PLA故障模型的基础上，我们对故障测试算法进行了详细的研究，对系统单故障和多故障的检测给出了必要的证明，并以此作为依据，产生出路由器系统常见故障的完全测试集，同时给出了故障测试算法的流程。
最后，我们在两个国家863重点任务中，以类PLA模型为指导，设计并实现了基于专用转发引擎和基于网络处理器的路由器硬件测试诊断系统。
High-performance network routers play an important role in the next generation high-speed IP network, their scales become larger and larger. Therefore, we need higher and higher reliability for router system. The technological approaches have only two: one is fault avoidance; and one is fault tolerance. The research for fault check and fault diagnosis must be taken into account to realize these two approaches.
Along with rapid development of micro-electronics technology, more and more Very Large Scale Integrate circuits are applied into router system, and this makes system more complex, and makes traditional fault diagnosis and reliability design more complex and more difficult.
The background for this research is "Experimental environment for Next Generation Internet" of 863. Aiming at the hardware architecture of high performance router system, we analyze and study the fault forms in router system carefully and set up relevant fault models for these forms, and we take fault models reduction into account. After analyzing the characteristics of all familiar faults carefully, we get their common characteristic and present one novel fault model which is analogous to PLA architecture. It comprise input line and output line and transfer line which connect input and output. This model simulate those likely faults which emerge in transfer process through connection of lines. Through reasonable hypothesis and demonstration, fault forms are standardized and reduced effectively on this model.
Based analogous PLA model, we make careful research on the algorithm of fault test, and present the relevant proof for single fault and multiple faults check of system. Then we come into being complete test set for familiar faults of router system and present the flow about this algorithm.
At last, we apply this algorithm into two significant tasks of 863. Based analogous PLA model, we design and implement two hardware test and diagnosis systems for router system based special forward engine and router system based network processor.
引文
[1] 邹逢兴主编，计算机应用系统的故障诊断与可靠性技术基础，北京：高等教育出版社，1999
[2] 杨士元编著，数字系统的故障诊断与可靠性设计，北京：清华大学出版社，1999
[3] Semiconductor Group, IEEE Standard 1149.1 (JTAG) Testability, TEXAS Instruments, 1997
[4] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE std. 1149.1-1990, IEEE Computer Society
[5] Torgny Schultz, Boundary Scan Test Bus IEEE 1149.1, School of Engineering Department of Electronic-and Computer Engineering
[6] Dave Bonnett, Guideline for Design of Boundary Scan Testing, Asset InterTech, Inc, 2002
[7] Adam Ley, Backplane System Testing, Asset InterTech, Inc, 2002
[8] Gerry Morgan, Some Board-Level DFT Guidelines of Boundary Scan Testing, Asset InterTech, Inc, 2002
[9] Michael Barr, Software-Based Memory Testing, Embedded Systems Academy, 2002
[10] 管剑波，崔向东，瞿国平，JTAG边界扫描技术在高速路由器硬件测试中的应用，上海：计算机工程，2001
[11] Jongchul Shin, Hyunjin Kim, Sungho Kang, At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks, Computer Systems Laboratory
[12] J. Christiansen, Testing of Integrated Circuits, CERN-EP/MIC
[13] Indradeep Ghosh, Sujit Dey, Niraj K. Jha, A Fast and Low Cost Testing Technique for Core-based System-on-Chip
[14] Xiaoliang Bai, Sujit Dey, High-level Crosstalk Defect Simulation for System-on-Chip Interconnects, ECE Department UC San Diego La Jolla
[15] Yervant Zorian, Erik Jan Marinissen, Sujit Dey, Testing Embedded-Core Based System Chips, Philips Research Dept. VLSI Design Automation & Test Prof. Holstlaan 4-WAY-41 5656 AA Eindhoven The Netherlands, 2001
[16] Amir Attarha, Mehrdad Nourani, Signal Integrity Fault Analysis Using Reduced Order Modeling, Center for Integrated Circuits & Systems The University of Texas at Dallas Richardson, 2001
[17] Vishal Anand, Designing for Flexibility, VLSI Technology (subsidiary of Philips Semiconductors), 2000
[18] Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki, Testing TAPed Cores and Wrapped CoresWith The Same Test Access Mechanism, LIP6 Laboratory
[19] Shihyu Yang, Chris Papachristou, Massood Tabib-Azar, Improving Bus Testing Via IDD Test and Boundary Scan, Department of Electrical Engineering and Computer Science Case Western Reserve University, 2002
[20] Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, An Investigation into Crosstalk Noise in DRAM Structures, Information Technology Laboratory University of Hanover, 2002
[21] Jon Turino, Built-in Self-Test Approaches for Mixed Signal ICs, Fluence Technology Incorporated Beaverton, 2002
[22] Erik Jan Marinissen, Robert Arendsen, Gerard Bos, A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, Philips Research Laboratories, 2002
[2] 杨士元编著，数字系统的故障诊断与可靠性设计，北京：清华大学出版社，1999
[3] Semiconductor Group, IEEE Standard 1149.1 (JTAG) Testability, TEXAS Instruments, 1997
[4] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE std. 1149.1-1990, IEEE Computer Society
[5] Torgny Schultz, Boundary Scan Test Bus IEEE 1149.1, School of Engineering Department of Electronic-and Computer Engineering
[6] Dave Bonnett, Guideline for Design of Boundary Scan Testing, Asset InterTech, Inc, 2002
[7] Adam Ley, Backplane System Testing, Asset InterTech, Inc, 2002
[8] Gerry Morgan, Some Board-Level DFT Guidelines of Boundary Scan Testing, Asset InterTech, Inc, 2002
[9] Michael Barr, Software-Based Memory Testing, Embedded Systems Academy, 2002
[10] 管剑波，崔向东，瞿国平，JTAG边界扫描技术在高速路由器硬件测试中的应用，上海：计算机工程，2001
[11] Jongchul Shin, Hyunjin Kim, Sungho Kang, At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks, Computer Systems Laboratory
[12] J. Christiansen, Testing of Integrated Circuits, CERN-EP/MIC
[13] Indradeep Ghosh, Sujit Dey, Niraj K. Jha, A Fast and Low Cost Testing Technique for Core-based System-on-Chip
[14] Xiaoliang Bai, Sujit Dey, High-level Crosstalk Defect Simulation for System-on-Chip Interconnects, ECE Department UC San Diego La Jolla
[15] Yervant Zorian, Erik Jan Marinissen, Sujit Dey, Testing Embedded-Core Based System Chips, Philips Research Dept. VLSI Design Automation & Test Prof. Holstlaan 4-WAY-41 5656 AA Eindhoven The Netherlands, 2001
[16] Amir Attarha, Mehrdad Nourani, Signal Integrity Fault Analysis Using Reduced Order Modeling, Center for Integrated Circuits & Systems The University of Texas at Dallas Richardson, 2001
[17] Vishal Anand, Designing for Flexibility, VLSI Technology (subsidiary of Philips Semiconductors), 2000
[18] Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki, Testing TAPed Cores and Wrapped CoresWith The Same Test Access Mechanism, LIP6 Laboratory
[19] Shihyu Yang, Chris Papachristou, Massood Tabib-Azar, Improving Bus Testing Via IDD Test and Boundary Scan, Department of Electrical Engineering and Computer Science Case Western Reserve University, 2002
[20] Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, An Investigation into Crosstalk Noise in DRAM Structures, Information Technology Laboratory University of Hanover, 2002
[21] Jon Turino, Built-in Self-Test Approaches for Mixed Signal ICs, Fluence Technology Incorporated Beaverton, 2002
[22] Erik Jan Marinissen, Robert Arendsen, Gerard Bos, A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, Philips Research Laboratories, 2002