嵌入式微处理器可测性设计研究与实现
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摘要
随着集成电路设计和制造技术的不断进步，芯片的集成度和复杂度也以惊人的速度发展。芯片测试遇到了前所未有的挑战，测试费用越来越高，出现了设计、生产费用与测试费用倒挂的局面。尤其是超深亚微米(VDSM)工艺的使用，生产过程中出现的故障也越来越多样、难测。在这种情况下，可测性设计(Design-For-Testability)技术成为解决芯片生产测试问题的主要手段之一，日益引起人们的重视。
可测性设计即调整电路的内部结构，使电路变得易测。本文针对嵌入式微处理器Estar1的结构特点，研究并实现了边界扫描、内部全扫描和内建自测试三种可测性设计技术，取得了良好的效果，故障覆盖率达到96％以上。
边界扫描测试是针对芯片的应用系统进行测试的，如PCB板测试。国际标准IEEE 1149.1规定了边界扫描的基本电路结构和功能。本文结合标准模块设计实现了Estar1的边界扫描结构，并进行了扩展，应用到芯片内部测试，节约了测试I/O口消耗，简化了测试过程。
内部扫描技术是为了克服时序电路由于状态很难确定所导致的测试复杂度而提出的一种技术，可以分为全扫描和部分扫描。本文根据Estar1的实际情况，设计实现了全扫描结构，既得到了较高的故障覆盖率，又对电路的延迟和芯片面积影响很小(延迟时间增加0.3％，芯片面积增加0.01％)。
内建自测试(Buit-In-Self-Test，BIST)技术被认为是解决由于电路集成度越来越大所造成的测试费用巨大和测试访问困难等问题的最有希望的技术。本文针对Estar1内部SSRAM的结构特点，实现了存储器自测试，得到了将近100％的故障覆盖率。
系统集成芯片(SoC，System-on-Chip)技术日新月异的发展受到了计算机界和电子工程界的普遍重视。SoC的测试问题由于第三方IP核的使用而显得特殊并复杂。本文对SoC的测试问题进行了初步研究，并介绍了嵌入式核测试标准IEEE P1500。
With the development of 1C desinging and manufacturing technology, the chip' s density and complexity also rises with the astonished rate. The testing of the chip is faced with very serious challenge, the cost of testing is always rising, and even larger than the designing and manufacturing cost. Especially with the use and advancement of VDSM(Very-Deep-Sub-Micron) technology, the faults during manufacturing become more multiple and difficult to test. " With the circumstance of all these things, l)FT(Design-For-Testability) technology become one of the main means to cult with the problem of chip manufacturing test and attract more and more attention.
Design For Testability means adjusting the structure of circuit and making the circuit easy to test. In this paper we investigate and carry out boundary scan ^ internal scan and built-in self-test three DFT technologies in the embedded microprocessor Estarl and get satisfying result, the fault coverage is more than 96%.
Boundary scan aims at the test of application system, e.g. PCB test. International standard IEEE 1149. 1 describes the basic circuit structure and performance of boundary scan. In this paper, we combine the standard modules realize the boundary scan of Estarl and also expand it to the test of internal circuit. This structure can save the I/O port of the chip and simplify the testing program.
Internal scan is advanced for the difficulty of fixing the state of sequential circuit, can be divided into full-scan and partial-scan. In this paper we use full-scan according to the real circumstance of Estarl and get high fault coverage with very little impact on the circuit.
Bult-In Self-Test is considered to be the most hopeful technology to solve the great cost and difficulty of manufacturing test because of the increasing of the circuit density. In this paper we use the BIST in the testing of the SSRAMs in Estarl according to the characteristics of the structure and get almost 100% fault coverage.
The rapid development of System-on-Chip(SoC) technology has been attracting more and more attention in computer and electronic engineering domain these years. The test of SoC is special and complex because the use of the IP core. In this paper, we investigate the problem of SoC test and introduce embedded core test international standard IEEE P1500.
可测性设计即调整电路的内部结构，使电路变得易测。本文针对嵌入式微处理器Estar1的结构特点，研究并实现了边界扫描、内部全扫描和内建自测试三种可测性设计技术，取得了良好的效果，故障覆盖率达到96％以上。
边界扫描测试是针对芯片的应用系统进行测试的，如PCB板测试。国际标准IEEE 1149.1规定了边界扫描的基本电路结构和功能。本文结合标准模块设计实现了Estar1的边界扫描结构，并进行了扩展，应用到芯片内部测试，节约了测试I/O口消耗，简化了测试过程。
内部扫描技术是为了克服时序电路由于状态很难确定所导致的测试复杂度而提出的一种技术，可以分为全扫描和部分扫描。本文根据Estar1的实际情况，设计实现了全扫描结构，既得到了较高的故障覆盖率，又对电路的延迟和芯片面积影响很小(延迟时间增加0.3％，芯片面积增加0.01％)。
内建自测试(Buit-In-Self-Test，BIST)技术被认为是解决由于电路集成度越来越大所造成的测试费用巨大和测试访问困难等问题的最有希望的技术。本文针对Estar1内部SSRAM的结构特点，实现了存储器自测试，得到了将近100％的故障覆盖率。
系统集成芯片(SoC，System-on-Chip)技术日新月异的发展受到了计算机界和电子工程界的普遍重视。SoC的测试问题由于第三方IP核的使用而显得特殊并复杂。本文对SoC的测试问题进行了初步研究，并介绍了嵌入式核测试标准IEEE P1500。
With the development of 1C desinging and manufacturing technology, the chip' s density and complexity also rises with the astonished rate. The testing of the chip is faced with very serious challenge, the cost of testing is always rising, and even larger than the designing and manufacturing cost. Especially with the use and advancement of VDSM(Very-Deep-Sub-Micron) technology, the faults during manufacturing become more multiple and difficult to test. " With the circumstance of all these things, l)FT(Design-For-Testability) technology become one of the main means to cult with the problem of chip manufacturing test and attract more and more attention.
Design For Testability means adjusting the structure of circuit and making the circuit easy to test. In this paper we investigate and carry out boundary scan ^ internal scan and built-in self-test three DFT technologies in the embedded microprocessor Estarl and get satisfying result, the fault coverage is more than 96%.
Boundary scan aims at the test of application system, e.g. PCB test. International standard IEEE 1149. 1 describes the basic circuit structure and performance of boundary scan. In this paper, we combine the standard modules realize the boundary scan of Estarl and also expand it to the test of internal circuit. This structure can save the I/O port of the chip and simplify the testing program.
Internal scan is advanced for the difficulty of fixing the state of sequential circuit, can be divided into full-scan and partial-scan. In this paper we use full-scan according to the real circumstance of Estarl and get high fault coverage with very little impact on the circuit.
Bult-In Self-Test is considered to be the most hopeful technology to solve the great cost and difficulty of manufacturing test because of the increasing of the circuit density. In this paper we use the BIST in the testing of the SSRAMs in Estarl according to the characteristics of the structure and get almost 100% fault coverage.
The rapid development of System-on-Chip(SoC) technology has been attracting more and more attention in computer and electronic engineering domain these years. The test of SoC is special and complex because the use of the IP core. In this paper, we investigate the problem of SoC test and introduce embedded core test international standard IEEE P1500.
引文
[1] 庄同曾 张安康 黄兰芳，“集成电路制造技术—原理与实践”，北京，电子工业出版社，1987
[2] 曾芷德，“数字系统测试与可测性”，长沙 国防科技大学出版社，1992
[3] "Boundary-Scan Tutorial", ASSET homepage: http://www. asset-intertech.com, ASSET InterTech, Inc., 2000
[4] "JTAG (IEEE 1149.1/P1149.4) Tutorial Introductory", 1997 TI Test Symposium
[5] 向东，“数字系统测试及测试性设计” 北京 科学出版社 1997
[6] "Built-in Self-Test" , http://www. ee. ncu. edu. tw
[7] Indradeep Ghosh, Anand Raghunathan, and Niraj K. Jha, " Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis", ICCD'95
[8] Hans-Joachim Wunderlich, "BIST FOR SYSTEMS-ON-A-CHIP", University of Stuttgart, 1998
[9] Wei-Cheng Lai, Kwang-Ting (Tim) Cheng, "Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip" , 2001, ACM
[10] 李华伟 李晓维 尹志刚 吕涛 何蓉晖，“可测试性设计技术在一款通用CPU芯片中的应用”，计算机工程与应用，2002．16，191～194
[11] "Microprocessor Test" , ECE 371EMR Microprocessor Verification, Test, and Design, Lecture 24
[12] 高树静 沈胜宇 李思昆 潘振宽，“嵌入式微处理器的可测性设计技术研究”，计算机工程与应用，2002年，16，218～222
[13] "BSDL File created/edited by Igor Mohor" http://www. opencores. org/cores/jtag/
[14] "DW_tapTAP Controller", Synopsys, Inc. 2000
[15] "DW_bc_1 Boundary Scan Cell Type BC_1" , Synopsys, Inc. 2000
[16] "Scan Synthesis Reference Manual" , Synopsys, Inc. 2000
[17] "Scan Synthesis User Guide" , Synopsys, Inc. 2000
[18] Mentor Graphics Corporation, "ASIC/IC Design-for-Test Process Guide" , 1997
[19] H.-J. Wunderlich, R. Dorsch, "Accumulator Based Deterministic BIST" Proc. IEEE International Test Conference, Washington D.C. Oct. (1998)
[20] Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana,"TAO-BIST: A Framework for Testability Analysis and Optimization of RTL Circuits for BIST" , Proc. 17th VLSI test symposium, 2000
[21] Jimmie Jonsson, "Memory Test" , University of Jonkoping, Sweden
[22] M.H. Tehranipour, Z. Navabi, S. M. Fakhraie, "A LOW-COST AT-SPEED BIST ARCHITECTURE FOR EMBEDDED PROCESSOR AND SRAM CORES" , The University of Tehran, Iran
[23] A. J. van de Goor I.B. S Tlili , "March tests for word-oriented memories " , Delft University of Technology Faculty of Information Technology and Systems Section Computer Architecture Digital Technique
[24] Y. Zorian, E. J. Marinissen and S. Dey. " Testing embeddedcore based system chips" , Proc. International Test Conference, 1998
[25] Dr R G "Ben" Bennetts, "IEEE P1500 Embedded Core Test Standard" , Bennetts AsSoCiates, 1 February, 2001
[26] "IEEE P1500 Standard for Embedded Core Test (SECT)" , http://grouper, ieee. org/groups/1500/
[27] Mehrdad Nourani, Christos Papachristou, "An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing " , Proc. International Test Conference, 2000
[28] Bulent I. Dervisoglu, "A Unified DFT Architecture for use with IEEE 1149． 1 and VSIA/IEEE P1500 Compliant Test Access Controllers" , Proc. International Test Conference, 2000
[2] 曾芷德，“数字系统测试与可测性”，长沙 国防科技大学出版社，1992
[3] "Boundary-Scan Tutorial", ASSET homepage: http://www. asset-intertech.com, ASSET InterTech, Inc., 2000
[4] "JTAG (IEEE 1149.1/P1149.4) Tutorial Introductory", 1997 TI Test Symposium
[5] 向东，“数字系统测试及测试性设计” 北京 科学出版社 1997
[6] "Built-in Self-Test" , http://www. ee. ncu. edu. tw
[7] Indradeep Ghosh, Anand Raghunathan, and Niraj K. Jha, " Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis", ICCD'95
[8] Hans-Joachim Wunderlich, "BIST FOR SYSTEMS-ON-A-CHIP", University of Stuttgart, 1998
[9] Wei-Cheng Lai, Kwang-Ting (Tim) Cheng, "Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip" , 2001, ACM
[10] 李华伟 李晓维 尹志刚 吕涛 何蓉晖，“可测试性设计技术在一款通用CPU芯片中的应用”，计算机工程与应用，2002．16，191～194
[11] "Microprocessor Test" , ECE 371EMR Microprocessor Verification, Test, and Design, Lecture 24
[12] 高树静 沈胜宇 李思昆 潘振宽，“嵌入式微处理器的可测性设计技术研究”，计算机工程与应用，2002年，16，218～222
[13] "BSDL File created/edited by Igor Mohor" http://www. opencores. org/cores/jtag/
[14] "DW_tapTAP Controller", Synopsys, Inc. 2000
[15] "DW_bc_1 Boundary Scan Cell Type BC_1" , Synopsys, Inc. 2000
[16] "Scan Synthesis Reference Manual" , Synopsys, Inc. 2000
[17] "Scan Synthesis User Guide" , Synopsys, Inc. 2000
[18] Mentor Graphics Corporation, "ASIC/IC Design-for-Test Process Guide" , 1997
[19] H.-J. Wunderlich, R. Dorsch, "Accumulator Based Deterministic BIST" Proc. IEEE International Test Conference, Washington D.C. Oct. (1998)
[20] Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana,"TAO-BIST: A Framework for Testability Analysis and Optimization of RTL Circuits for BIST" , Proc. 17th VLSI test symposium, 2000
[21] Jimmie Jonsson, "Memory Test" , University of Jonkoping, Sweden
[22] M.H. Tehranipour, Z. Navabi, S. M. Fakhraie, "A LOW-COST AT-SPEED BIST ARCHITECTURE FOR EMBEDDED PROCESSOR AND SRAM CORES" , The University of Tehran, Iran
[23] A. J. van de Goor I.B. S Tlili , "March tests for word-oriented memories " , Delft University of Technology Faculty of Information Technology and Systems Section Computer Architecture Digital Technique
[24] Y. Zorian, E. J. Marinissen and S. Dey. " Testing embeddedcore based system chips" , Proc. International Test Conference, 1998
[25] Dr R G "Ben" Bennetts, "IEEE P1500 Embedded Core Test Standard" , Bennetts AsSoCiates, 1 February, 2001
[26] "IEEE P1500 Standard for Embedded Core Test (SECT)" , http://grouper, ieee. org/groups/1500/
[27] Mehrdad Nourani, Christos Papachristou, "An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing " , Proc. International Test Conference, 2000
[28] Bulent I. Dervisoglu, "A Unified DFT Architecture for use with IEEE 1149． 1 and VSIA/IEEE P1500 Compliant Test Access Controllers" , Proc. International Test Conference, 2000