无线传感器网络节点芯片关键技术的研究与实现
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摘要
无线传感器网络是新兴学科与传统学科领域交叉的结果。它在环境监测、高效农业、工业控制、医疗护理、物流管理、军事领域都有极强的应用潜力。随着无线传感器网络的逐步应用,对低成本、低功耗高集成度的无线传感器网络节点SOC芯片需求越来越迫切,本论文系统地论述了无线传感器网络节点SOC基带芯片关键技术的研究与实现。
首先,从无线传感器网络节点SOC芯片的体系架构上,对低成本、低功耗以及高性能等几个关键技术进行了尝试,除采用动态功耗管理技术以降低功耗外,在兼容标准51指令集的前提下,对传统8051 MCU核架构进行了改进,采用指令与数据并行总线,实现二级流水技术,以传统8051的低成本获得了性能10倍的提高,实现了指令单周期的处理能力;同时,为了实现芯片的低成本,片上集成的内存容量受限,为了在有限的内存条件下,不影响芯片SOC系统的实际使用性能,本文设计出了灵活、可配置分布式的存储空间管理映射方式。
接着,在具体电路设计过程中,围绕低成本、低功耗、高性能等关键技术进行了详细的论述。
在物理层电路实现时,改进了传统SOC集成的电源管理电路LDO结构,增加了正反馈环路来采样输出电流,提高了电路的瞬态响应,同时,为了降低电源管理模块自身能量的消耗,实现了工作于亚域值区的基准电路;另外,在深入分析了晶体振荡器频率与环境温度的偏移曲线后,采用查找表原理,设计出校准分频链电路,实现了SOC芯片时钟信号产生电路的自校准功能,提高了SOC芯片输入时钟信号的精度。
在MAC层电路实现时,在研究了无线传感器网络冲突避免载波监听多点接入CSMA/CA算法后,除了采用软硬件协同设计的方法,还进行了基于协处理器结构的相关优化,通过控制寄存器RNDH和RNDL,实现了5位伪随机码生成器和16位CRC校验电路的可复用结构;另外,针对现有S盒电路设计的不足,建立了AES协处理器的功耗攻击模型,采用随机异构S盒的字节替换单元,改进了AES协处理器的设计,增强了AES的抗功耗攻击能力,从而实现节点芯片的高安全性。
在论文的最后,讨论了该SOC芯片数字逻辑电路和嵌入式内存的低功耗测试技术,同时,根据软硬协同验证的思想方法,建立了该SOC芯片各阶段相应的验证方案,完成了无线传感器网络节点SOC芯片的FPGA验证。
Wireless Sensor Network(WSN)has been widely applied in military purposes, environmental monitoring and forecast, security surveillance and so on. With the rapid development of modern silicon technology and Very Large Scale Integration (VLSI) technology, it is possible to integrate different circuits into one single chip, as a WSN node SOC solution. As the requirements of complex applications growing rapidly, the need for high performance is increasing as well as low cost, while the low power consumption is also a key issue. In this thesis, several key technologies of WSN node SOC are investigated.
At architecture design level, several key technologies are described in detail. Besides using dynamic power management technology to reduce power consumption, the embedded 8-bit Micro Control Unit (MCU) is optimized by independent instruction bus and data bus, and a two-stage pipeline feature is added to achieve low-cost and high-performance. Compared with the existing standard 8051 core, the enhanced one-cycle MCU is still compatible with standard 51 instruction sets, while providing ten times efficiency. Moreover, in order to achieve more program and data storage space without increasing the volume of physical memories, a configurable distributed memory mapping method is employed.
On following specific circuits design plot, some key technologies are adopted. In physical layer circuit, aim to improve the embedded LDO (low dropout regulator) system stability, we implement a dual-loop structure, and add a positive feedback loop to accelerate the circuit transient response. In order to reduce power consumption, the referenced circuit is designed to operate on the subthreshold region other than the traditionally used saturation region; Meanwhile, after analyzing the curve characteristics of crystal oscillator frequency offset and temperature, we resort to a self-calibration algorithm based on divide-frequency chain, the self-calibration circuit is implemented by a series of look up table registers that trim the input clock frequency for this SOC chip.
As to MAC layer circuit, to achieve the required speed for resource-limited embedded applications, a novel CSMA/CA coprocessor is implemented, based on IEEE 802.15.4 protocol and CSMA/CA algorithm for channels’competitive access. The CSMA/CA coprocessor is designed to cooperate with the enhanced 8-bit 8051 microcontroller, using independent instruction sets to control the RF access flow by software. A Pseudo-random number generator circuit and a CRC circuit are reused through assigning different value to two registers: RNDH and RNDL. Toward the limitations of existing S-box circuit, a power attack model of AES coprocessor is established, and a novel byte substitution circuit is proposed against CPA attack, using inhomogeneous S-boxes rather than fixed S-boxes.
Finally, in order to achieve high fault coverage, and with low test power at the same time, different low-power DFT techniques are adopted for different circuits. By the method of hardware and software co-verification, a FPGA verification platform to communicate with CC2420 is presented.
首先,从无线传感器网络节点SOC芯片的体系架构上,对低成本、低功耗以及高性能等几个关键技术进行了尝试,除采用动态功耗管理技术以降低功耗外,在兼容标准51指令集的前提下,对传统8051 MCU核架构进行了改进,采用指令与数据并行总线,实现二级流水技术,以传统8051的低成本获得了性能10倍的提高,实现了指令单周期的处理能力;同时,为了实现芯片的低成本,片上集成的内存容量受限,为了在有限的内存条件下,不影响芯片SOC系统的实际使用性能,本文设计出了灵活、可配置分布式的存储空间管理映射方式。
接着,在具体电路设计过程中,围绕低成本、低功耗、高性能等关键技术进行了详细的论述。
在物理层电路实现时,改进了传统SOC集成的电源管理电路LDO结构,增加了正反馈环路来采样输出电流,提高了电路的瞬态响应,同时,为了降低电源管理模块自身能量的消耗,实现了工作于亚域值区的基准电路;另外,在深入分析了晶体振荡器频率与环境温度的偏移曲线后,采用查找表原理,设计出校准分频链电路,实现了SOC芯片时钟信号产生电路的自校准功能,提高了SOC芯片输入时钟信号的精度。
在MAC层电路实现时,在研究了无线传感器网络冲突避免载波监听多点接入CSMA/CA算法后,除了采用软硬件协同设计的方法,还进行了基于协处理器结构的相关优化,通过控制寄存器RNDH和RNDL,实现了5位伪随机码生成器和16位CRC校验电路的可复用结构;另外,针对现有S盒电路设计的不足,建立了AES协处理器的功耗攻击模型,采用随机异构S盒的字节替换单元,改进了AES协处理器的设计,增强了AES的抗功耗攻击能力,从而实现节点芯片的高安全性。
在论文的最后,讨论了该SOC芯片数字逻辑电路和嵌入式内存的低功耗测试技术,同时,根据软硬协同验证的思想方法,建立了该SOC芯片各阶段相应的验证方案,完成了无线传感器网络节点SOC芯片的FPGA验证。
Wireless Sensor Network(WSN)has been widely applied in military purposes, environmental monitoring and forecast, security surveillance and so on. With the rapid development of modern silicon technology and Very Large Scale Integration (VLSI) technology, it is possible to integrate different circuits into one single chip, as a WSN node SOC solution. As the requirements of complex applications growing rapidly, the need for high performance is increasing as well as low cost, while the low power consumption is also a key issue. In this thesis, several key technologies of WSN node SOC are investigated.
At architecture design level, several key technologies are described in detail. Besides using dynamic power management technology to reduce power consumption, the embedded 8-bit Micro Control Unit (MCU) is optimized by independent instruction bus and data bus, and a two-stage pipeline feature is added to achieve low-cost and high-performance. Compared with the existing standard 8051 core, the enhanced one-cycle MCU is still compatible with standard 51 instruction sets, while providing ten times efficiency. Moreover, in order to achieve more program and data storage space without increasing the volume of physical memories, a configurable distributed memory mapping method is employed.
On following specific circuits design plot, some key technologies are adopted. In physical layer circuit, aim to improve the embedded LDO (low dropout regulator) system stability, we implement a dual-loop structure, and add a positive feedback loop to accelerate the circuit transient response. In order to reduce power consumption, the referenced circuit is designed to operate on the subthreshold region other than the traditionally used saturation region; Meanwhile, after analyzing the curve characteristics of crystal oscillator frequency offset and temperature, we resort to a self-calibration algorithm based on divide-frequency chain, the self-calibration circuit is implemented by a series of look up table registers that trim the input clock frequency for this SOC chip.
As to MAC layer circuit, to achieve the required speed for resource-limited embedded applications, a novel CSMA/CA coprocessor is implemented, based on IEEE 802.15.4 protocol and CSMA/CA algorithm for channels’competitive access. The CSMA/CA coprocessor is designed to cooperate with the enhanced 8-bit 8051 microcontroller, using independent instruction sets to control the RF access flow by software. A Pseudo-random number generator circuit and a CRC circuit are reused through assigning different value to two registers: RNDH and RNDL. Toward the limitations of existing S-box circuit, a power attack model of AES coprocessor is established, and a novel byte substitution circuit is proposed against CPA attack, using inhomogeneous S-boxes rather than fixed S-boxes.
Finally, in order to achieve high fault coverage, and with low test power at the same time, different low-power DFT techniques are adopted for different circuits. By the method of hardware and software co-verification, a FPGA verification platform to communicate with CC2420 is presented.
引文
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