低压高性能采样/保持电路的研究
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摘要
伴随数字工艺Scaling技术的不断发展和片上系统集成的需求，低压技术成为实现高端模数转换器(Analog-to-Digital Converter)ADC的发展趋势之一。与此同时，高清数字视频和无线射频技术的进步对ADC速度和精度也提出了更高要求。因此，研究对ADC系统速度、精度和功耗有着重要影响的采样／保持(Sample and Hold)S／H模块如何在低压下达到高性能成为热门课题。
本文源于S／H基本理论，从采样开关、跨导放大器(Operational TransconductanceAmplifier)OTA和S／H电路拓扑结构三个方面研究和探讨了在低压工艺下实现高性能S／H电路的难点和相关技术方法，并基于SMIC Si 0．18μm CMOS工艺模型进行了设计和验证。
首先，推导了电源电压V_(DD)按比例减小的情况下S／H电路各主要参数之间的制约关系：要保持精度N不变，电路允许的最小噪声电压σ也必须按比例减小，由带宽GBW和采样率f_s决定的速度均需不同程度下降；当工艺线宽L、GBW、f_s和N均恒定时，功耗反而会上升，要降低功耗则要牺牲速度和精度；当深亚微米工艺中L足够小使V_(DD)随之线性减小时，功耗在GBW、f_s、N恒定情况下降低。
其次，在对比总结采样开关各种非理想因素及其相关解决技术基础上，提出了一种高线性度无馈通双边对称(No-Feedthrough Double-Side Symmetrical)NFDSS栅压自举NMOS采样开关；在1．8V电源电压下，仿真测试了8种类型采样开关并比较其在满摆幅输入下导通电阻R_(on)曲线，得到该NFDSS开关具有仅不足4Ω最小且最稳定的R_(on)，更适合低压高性能应用。
接着，通过求证适合高性能S／H系统OTA的增益自举和无电容前馈补偿技术增益带宽设计规则，提出了一种高增益大带宽大摆幅的共源共栅跨导前馈补偿(Cascode Gm-FeedForwrd)CGFF两级全差分OTA，其性能优于传统套筒式、折叠式共源共栅Cascode-OTA和Miller补偿两级OTA。
然后，从分析相关双采样(Correlated Double Sampling)CDS原理和比较不同CDS技术入手，揭示了它与S／H原理的相关性，并将同向宽带CDS原理应用于传统电荷转移型S／H电路，获得能消除OTA失调、低频噪声和开关电荷注入等直流误差且增益误差远低于传统值的CDS-S／H拓扑。
最后，综合前述不同技术，在3．3V电源电压下，提出了12bit精度100Msps采样率S／H电路的3例设计方案。优化的仿真结果表明：应用NFDSS栅压自举采样开关和增益95．47dB带宽760MHz相位裕度59．56°增益自举OTA的方案Ⅰ得到了84．24dB-SFDR；仅替换90．39dB增益726．9MHz带宽CGFF-OTA的方案Ⅱ比方案Ⅰ功耗低10．69mW且平台稳定时间长6．3％；改用CDS-S／H拓扑结构的方案Ⅲ相比方案Ⅰ与Ⅱ有最小增益误差0．1199‰，OTA结构最为简单，增益仅需69．96dB。
3例方案均实现了12bit、100Msps S／H电路，验证了本文提出技术方法的可行性，从不同角度克服了S/H电路精度N、带宽GBW、采样率f_s和功耗等指标之间相互制约的性能瓶颈，为解决低压带来的设计难题提供了可选途径。
上述理论和方法可望用于高性能流水线Pipeline ADC的前端S／H模块实现和相关技术领域的进一步研究探讨。
With the continued developing of digital process scaling down and the demand of system-on-chip, low-voltage technology has became one of the trends of achieving high-end Analog-to-Digital Converters (ADC). At the same time, progress of high-definition television and wireless radiofrequency technologies has also requested higher ADC's speed and accuracy. So, study of low-voltage high-performance Sample-and-Hold(S/H) module which has an important impact of ADC's speed, resolution and power dissipation is a hot subject.
In this thesis, stemming from S/H basic theory, the difficulties and related technical methods of achieving high-performance S/H circuit under low-voltage are researched and discussed from three areas which are sampling switch, Operational Transconductance Amplifier (OTA) and S/H circuit topology, and, designs and authentications are also gived based on SMIC Si 0.18μm CMOS process.
Firstly, the constrained interactions between several main parameters of S/H circuits and the declining supply voltage V_(DD) are derived. If resolution N is kept constant, the minimum limited noise voltageσmust be lower, and speed determined by either bandwidth GBW ox sampling frequency f_s will drop by different levels. Power dissipation will rise inversely if all of process linewidth L, N, GBW and f_s are kept constant, so speed and resolution need to be sacrificed to save the power. In deep sub-micro process power dissipation will be reduced if all of N, GBW and f_s are kept constant when L is small enough that V_(DD) scales down linearly with it.
Secondly, on the basis of aggregating and comparing main non-ideal factors and relative technical solution, a high-linearity No-Feedthrough Double-Side Symmetrical (NFDSS) gate-voltage bootstrapped sampling switch is presented. By testing eight different kinds of switches in simulation under 1.8V-supply voltage and comparing the curve of the on-state resistant R_(on) with full-swing input, it is got that this NFDSS switch with R_(on) less than 4Ωwhich is the smallest and the most stable of all is more suitable for low-voltage high-performance applications.
Thirdly, by the confirmation of the gain-bandwidth design rules of gain-boost and no-capacitor feedforward compensation technology of OTA suitable for high-performance S/H system, a high-gain wide-band large-swing Cascode Gm-FeedForwrd (CGFF) two-stage differential OTA is proposed, of which the performance is better than that of traditional telescope or folded cascode OTA and Miller compensation two-stage OTA.
Then, from Correlated Double Sampling (CDS) theory and comparative analysis of different CDS technologies, the correlation in the principle with S/H is revealed, and, a CDS-S/H topology is got from a traditional charge-transferring S/H topology combined with a noninverting wide-band CDS topology, which can cancel the dc error such as OTA's offset, low frequency noise and charge injection of switches and achieve much lower gain-error synchronously.
Finally, three design strategies are also proposed for 12bit-resolution 100Msps-speed S/H circuit by different configurations with the above modules under 3.3V-supply voltage. The optimized simulation results show that strategy I of the NFDSS gate-voltage bootstrapped sampling switch and 95.47dB-gain 760MHz-bandwidth 59.56°-phase margin gainboost cascode OTA attains 84.24dB-SFDR, strategy II has 10.69mW lower power dissipation and 6.3% longer hold time than strategy I with the replacement of the 90.39dB-gain 726.9MHz-bandwidth CGFF-OTA, and, by using the CDS-S/H topology, strategy HI gets the smallest gain-error 0.1199%o, of which the OTA is the simplest and only needs 69.96dB-gain.
So, all of the three strategies have achieved 12bit 100Msps S/H circuit and verified the feasibility of the technical methods introduced in mis paper, which overcome the performance bottleneck of the constrained interactions between specifications such as N, GBW,f_s, power dissipation et al. from different angles and offer some optional ways towards solving design problems caused by low-voltage.
The above theory and methodology are suitable for the front-end S/H module of high-performance pipeline ADC and further research and discussion of relative technical aspects.
本文源于S／H基本理论，从采样开关、跨导放大器(Operational TransconductanceAmplifier)OTA和S／H电路拓扑结构三个方面研究和探讨了在低压工艺下实现高性能S／H电路的难点和相关技术方法，并基于SMIC Si 0．18μm CMOS工艺模型进行了设计和验证。
首先，推导了电源电压V_(DD)按比例减小的情况下S／H电路各主要参数之间的制约关系：要保持精度N不变，电路允许的最小噪声电压σ也必须按比例减小，由带宽GBW和采样率f_s决定的速度均需不同程度下降；当工艺线宽L、GBW、f_s和N均恒定时，功耗反而会上升，要降低功耗则要牺牲速度和精度；当深亚微米工艺中L足够小使V_(DD)随之线性减小时，功耗在GBW、f_s、N恒定情况下降低。
其次，在对比总结采样开关各种非理想因素及其相关解决技术基础上，提出了一种高线性度无馈通双边对称(No-Feedthrough Double-Side Symmetrical)NFDSS栅压自举NMOS采样开关；在1．8V电源电压下，仿真测试了8种类型采样开关并比较其在满摆幅输入下导通电阻R_(on)曲线，得到该NFDSS开关具有仅不足4Ω最小且最稳定的R_(on)，更适合低压高性能应用。
接着，通过求证适合高性能S／H系统OTA的增益自举和无电容前馈补偿技术增益带宽设计规则，提出了一种高增益大带宽大摆幅的共源共栅跨导前馈补偿(Cascode Gm-FeedForwrd)CGFF两级全差分OTA，其性能优于传统套筒式、折叠式共源共栅Cascode-OTA和Miller补偿两级OTA。
然后，从分析相关双采样(Correlated Double Sampling)CDS原理和比较不同CDS技术入手，揭示了它与S／H原理的相关性，并将同向宽带CDS原理应用于传统电荷转移型S／H电路，获得能消除OTA失调、低频噪声和开关电荷注入等直流误差且增益误差远低于传统值的CDS-S／H拓扑。
最后，综合前述不同技术，在3．3V电源电压下，提出了12bit精度100Msps采样率S／H电路的3例设计方案。优化的仿真结果表明：应用NFDSS栅压自举采样开关和增益95．47dB带宽760MHz相位裕度59．56°增益自举OTA的方案Ⅰ得到了84．24dB-SFDR；仅替换90．39dB增益726．9MHz带宽CGFF-OTA的方案Ⅱ比方案Ⅰ功耗低10．69mW且平台稳定时间长6．3％；改用CDS-S／H拓扑结构的方案Ⅲ相比方案Ⅰ与Ⅱ有最小增益误差0．1199‰，OTA结构最为简单，增益仅需69．96dB。
3例方案均实现了12bit、100Msps S／H电路，验证了本文提出技术方法的可行性，从不同角度克服了S/H电路精度N、带宽GBW、采样率f_s和功耗等指标之间相互制约的性能瓶颈，为解决低压带来的设计难题提供了可选途径。
上述理论和方法可望用于高性能流水线Pipeline ADC的前端S／H模块实现和相关技术领域的进一步研究探讨。
With the continued developing of digital process scaling down and the demand of system-on-chip, low-voltage technology has became one of the trends of achieving high-end Analog-to-Digital Converters (ADC). At the same time, progress of high-definition television and wireless radiofrequency technologies has also requested higher ADC's speed and accuracy. So, study of low-voltage high-performance Sample-and-Hold(S/H) module which has an important impact of ADC's speed, resolution and power dissipation is a hot subject.
In this thesis, stemming from S/H basic theory, the difficulties and related technical methods of achieving high-performance S/H circuit under low-voltage are researched and discussed from three areas which are sampling switch, Operational Transconductance Amplifier (OTA) and S/H circuit topology, and, designs and authentications are also gived based on SMIC Si 0.18μm CMOS process.
Firstly, the constrained interactions between several main parameters of S/H circuits and the declining supply voltage V_(DD) are derived. If resolution N is kept constant, the minimum limited noise voltageσmust be lower, and speed determined by either bandwidth GBW ox sampling frequency f_s will drop by different levels. Power dissipation will rise inversely if all of process linewidth L, N, GBW and f_s are kept constant, so speed and resolution need to be sacrificed to save the power. In deep sub-micro process power dissipation will be reduced if all of N, GBW and f_s are kept constant when L is small enough that V_(DD) scales down linearly with it.
Secondly, on the basis of aggregating and comparing main non-ideal factors and relative technical solution, a high-linearity No-Feedthrough Double-Side Symmetrical (NFDSS) gate-voltage bootstrapped sampling switch is presented. By testing eight different kinds of switches in simulation under 1.8V-supply voltage and comparing the curve of the on-state resistant R_(on) with full-swing input, it is got that this NFDSS switch with R_(on) less than 4Ωwhich is the smallest and the most stable of all is more suitable for low-voltage high-performance applications.
Thirdly, by the confirmation of the gain-bandwidth design rules of gain-boost and no-capacitor feedforward compensation technology of OTA suitable for high-performance S/H system, a high-gain wide-band large-swing Cascode Gm-FeedForwrd (CGFF) two-stage differential OTA is proposed, of which the performance is better than that of traditional telescope or folded cascode OTA and Miller compensation two-stage OTA.
Then, from Correlated Double Sampling (CDS) theory and comparative analysis of different CDS technologies, the correlation in the principle with S/H is revealed, and, a CDS-S/H topology is got from a traditional charge-transferring S/H topology combined with a noninverting wide-band CDS topology, which can cancel the dc error such as OTA's offset, low frequency noise and charge injection of switches and achieve much lower gain-error synchronously.
Finally, three design strategies are also proposed for 12bit-resolution 100Msps-speed S/H circuit by different configurations with the above modules under 3.3V-supply voltage. The optimized simulation results show that strategy I of the NFDSS gate-voltage bootstrapped sampling switch and 95.47dB-gain 760MHz-bandwidth 59.56°-phase margin gainboost cascode OTA attains 84.24dB-SFDR, strategy II has 10.69mW lower power dissipation and 6.3% longer hold time than strategy I with the replacement of the 90.39dB-gain 726.9MHz-bandwidth CGFF-OTA, and, by using the CDS-S/H topology, strategy HI gets the smallest gain-error 0.1199%o, of which the OTA is the simplest and only needs 69.96dB-gain.
So, all of the three strategies have achieved 12bit 100Msps S/H circuit and verified the feasibility of the technical methods introduced in mis paper, which overcome the performance bottleneck of the constrained interactions between specifications such as N, GBW,f_s, power dissipation et al. from different angles and offer some optional ways towards solving design problems caused by low-voltage.
The above theory and methodology are suitable for the front-end S/H module of high-performance pipeline ADC and further research and discussion of relative technical aspects.
引文
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