高速串行RapidIO中CDR的关键电路设计
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摘要
在高速串行RapidIO数据通信中,作为一种基于可靠性的开放式互连协议标准,RapidIO以其高效率、高稳定性、低系统成本的特点,为通信系统各器件间提供了高带宽、低延时数据传输的解决方案。由于时钟抖动、偏斜、队列间同步以及串扰噪声等各种非理想因素的影响,同时考虑到硬件开销,一般只传送数据信号而不传送与数据信号同步的时钟信号。为了保证接受端的数据同步问题,采用了时钟数据恢复电路(CDR)技术。
本文在对RapidIO互联规范理解的基础上,根据RapidIO互连规范对CDR的性能要求,在0.13um CMOS工艺下设计实现了面向RapidIO应用的CDR关键电路。本文的主要工作以及创新之处包括以下几方面:
1.通过对CDR的几种实现结构的研究和比较,以及考虑到设计中的速度、抖动性和稳定性的最大设计限度,本文采用了基于锁相环结构的CDR,结合相位选择插值技术和多重相位技术来实现时钟数据的恢复。
2.考虑到环路的稳定性和速度,对鉴相器和电荷泵进行了设计改进,使鉴相器的死区和一般电荷泵的非理想特性得到很好解决,并通过Hspice模拟验证。
3.对多相时钟产生机制的深入研究,设计了基于单端环形结构的振荡器,将3级结构和5级结构的VCO进行环路嵌套,实现八相等相位差的时钟信号,相邻两相相位差为π/4。
4.遵循高速数模混合电路版图设计准则,完成了CDR核心模块的版图实现。电路的模拟结果显示该设计实现的CDR满足了串行RapidIO互连规范的传输要求。
In the high-speed serial RapidIO data communication, as an opening interconnect protocol standards which based on reliability, RapidIO features in its high efficiency, excellent stability and low system cost, which provides a smart data transmission solution with high-bandwidth and low-latency for the communication between devices in systems. Considering the various non-ideal factors including the clock jitter, skew, queue synchronization and crosstalk noise, and along with the hardware cost, it generally transmits data signals instead of clock signals which synchronized with the data signal. In order to ensure the data synchronization problems of the receiver, we employ the clock and date recovery circuit (CDR) technology.
The paper based on the interpretation of RapidIo interconnect architecture, with regard to the performance requirements of CDR, successfully explored critical circuit of CDR with the 0.13um CMOS technology, which is mainly applied to the high-speed serial RapidIO.
The major contents and highlights of the research are as follows:
(1) Through the study and comparison of several different kinds of CDR, and with consideration of the maximum design limits of speed, jitter and stability , The paper employ a CDR which based on PLL structure , combined with phase select interpolation technology and multi-phase technology to realize the clock signal recovery.
(2) Taking stability and speed into account, we bettered the design of charge pump and voltage controlled oscillator, thereby the dead-region of FD and the non-ideal characteristics of common charge pump would get a preferable solution, and get through the Hspice simulate verification.
(3) With in-depth research on the multiphase clock generation mechanism, design an oscillator which based on single-ended ring structure, nesting the VCO which has the three-grade structure and five-grade structure into loop structure, so as to achieve a clock signal with eight-phase equal phase difference ,whose adjacent phase difference isπ/4.
(4) obey the high-speed digital hybrid circuit layout guidelines, realizing the layout design of the core CDR modules. The simulation results of circuit well satisfy the demands of the serial RapidIo interconnect architecture transmission requirements.
本文在对RapidIO互联规范理解的基础上,根据RapidIO互连规范对CDR的性能要求,在0.13um CMOS工艺下设计实现了面向RapidIO应用的CDR关键电路。本文的主要工作以及创新之处包括以下几方面:
1.通过对CDR的几种实现结构的研究和比较,以及考虑到设计中的速度、抖动性和稳定性的最大设计限度,本文采用了基于锁相环结构的CDR,结合相位选择插值技术和多重相位技术来实现时钟数据的恢复。
2.考虑到环路的稳定性和速度,对鉴相器和电荷泵进行了设计改进,使鉴相器的死区和一般电荷泵的非理想特性得到很好解决,并通过Hspice模拟验证。
3.对多相时钟产生机制的深入研究,设计了基于单端环形结构的振荡器,将3级结构和5级结构的VCO进行环路嵌套,实现八相等相位差的时钟信号,相邻两相相位差为π/4。
4.遵循高速数模混合电路版图设计准则,完成了CDR核心模块的版图实现。电路的模拟结果显示该设计实现的CDR满足了串行RapidIO互连规范的传输要求。
In the high-speed serial RapidIO data communication, as an opening interconnect protocol standards which based on reliability, RapidIO features in its high efficiency, excellent stability and low system cost, which provides a smart data transmission solution with high-bandwidth and low-latency for the communication between devices in systems. Considering the various non-ideal factors including the clock jitter, skew, queue synchronization and crosstalk noise, and along with the hardware cost, it generally transmits data signals instead of clock signals which synchronized with the data signal. In order to ensure the data synchronization problems of the receiver, we employ the clock and date recovery circuit (CDR) technology.
The paper based on the interpretation of RapidIo interconnect architecture, with regard to the performance requirements of CDR, successfully explored critical circuit of CDR with the 0.13um CMOS technology, which is mainly applied to the high-speed serial RapidIO.
The major contents and highlights of the research are as follows:
(1) Through the study and comparison of several different kinds of CDR, and with consideration of the maximum design limits of speed, jitter and stability , The paper employ a CDR which based on PLL structure , combined with phase select interpolation technology and multi-phase technology to realize the clock signal recovery.
(2) Taking stability and speed into account, we bettered the design of charge pump and voltage controlled oscillator, thereby the dead-region of FD and the non-ideal characteristics of common charge pump would get a preferable solution, and get through the Hspice simulate verification.
(3) With in-depth research on the multiphase clock generation mechanism, design an oscillator which based on single-ended ring structure, nesting the VCO which has the three-grade structure and five-grade structure into loop structure, so as to achieve a clock signal with eight-phase equal phase difference ,whose adjacent phase difference isπ/4.
(4) obey the high-speed digital hybrid circuit layout guidelines, realizing the layout design of the core CDR modules. The simulation results of circuit well satisfy the demands of the serial RapidIo interconnect architecture transmission requirements.
引文
[1]利用串行RapidIO连接功能增强DSP协处理能力.http://www.eaw.com.cn
[2] RapidIO嵌入式系统互连总线概述.http://www.rte-sky.com
[3] Serial RapidIO 2.1 IP Core. http://www.lattice.com
[4] Mehrdad Ramezani. Gigabit per second Clock and Data Recovery Circuits for Local Area Networks University of Toronto, 2004
[5] Jafar Savoj. A 10-Gb/s CMOS Clock and Data Recovery Circuit University of California, Los Angeles, 2001
[6] Jun Cao. Clock Multiplier Unit and Clock Data Recovery Circuit for 10Gb/s Broadband Communication in 0.18μm CMOS, Irvine 2003
[7] RapidIO Technology White Paper. http://www.rapidio.org
[8]裴济杰. RapidIO成就高速互连之美. 2005
[9] Sam Fuller等著,王勇等译. RapidIO嵌入式系统互连.北京:电子工业出版社, 2006.6
[10] RapidIO Trade Association. RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 2.1, 2009.08
[11] Cattalen, Pelard, et al. Realization of multi-gigabit channel equalization and crosstalk cancellation integrated circuits. IEEE Journal of Solid-State Circuits, 2004,39(10):1659-1669
[12] J. Caroselli, C. Liu. An Analytic System Model for High-Speed Interconnects and its Application to the Specification of Signaling and Equalization Architectures for 10Gbps Backplane Communication. IEC DesignCon 2006, 2006.01
[13] Kreien K. Iniewski, R. Badalone, M. Lapointe, M. Syrzycki. SERDES Technology for Gigabit I/O Communications in Storage Area Networking. IWSOC'04 IEEE, 2004
[14] Dengpeng Chen, Zhongxiang Shen. Bi-directional coupling between two coupled transmission lines. IEEE Microwave and Wireless Components Letters, 2003,13(12):514-516
[15] kamp.R,Langmann.U,Zimmermann.C. A 10Gb/s CMOS Clock and Data Recovery Circuit with all Analog Phase Interpolator[J].IEEE Journal of Solid State Circuits,2005,40,(3)
[16] B.Razavi,Challenges in the Design of High-Speed Clock Data Recovery Circuit IEEE
[17] Chin-Sheng Chen, Chang,R.C.A new prescaler for fully integrated 5-GHz MOS frequency synthesizer Circuits and Systems, 2004. ISCAS '04. Proce of the 2004 International Symposium on ,Volume: 4, May 2004 , 23-26
[18] S.Sidiropoulos. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers. IEEE Symp.VLSI Circuits, 2003:185-188
[19] A CMOS mixed signal clock and data recovery circuit for PCEI 6G backplane transceiver.IEEE J Solid State Cireuits,2006,41:597
[20] Wang Huan,Wang Zhigong,Feng Jun,Xiong Mingzhen,Zhang Li.2.488 Gbit/s clock and data recovery circuit in 0.35um CMOS in Joumal of southeast University,2006,pp 143-147.
[21] Hyung-Wook Jang , Sung-Sop Lee, Jin-Ku Kang A Clock Recovery Circuit using Half-rate 4X oversampling PD
[22] Phase Interpolator Based CDR, http://www.rambus.com
[23] S. I. Ahmed Tad A. Kwasniewski ,Overview of oversampling clock and data recovery circuits
[24] Cheng, et al.A Fast-Lock DLL with Power-On Reset Circuit, IEICE Trans on Fundamentals, Vol.E87-A No.9, pp.2210-2220, Sep. 2004.
[25] Saleem Mukhtar.Interval Modulation:A New Paradigm for the Design of Hish Speed Communication Systems [Z].Pasadena:California Institute of Technology,2004
[26] Behzad Razavi,Challenges in the Design of High-Speed Clock and Data Recovery Circuits, IEEE Communication Magazine,vol.40,Aug.2002, pp.94-101
[27] Lu Ping,Ye Fan and Ren Junyan,A Low-Jitter Frequency Synthesizer with Dynamic PhaseInterpolation for High-Speed Ethemet,IEEE,2006
[28] Hyung-Wook Jang , Sung-Sop Lee, Jin-Ku Kang. A Clock Recovery Circuit using Half-rate 4X oversampling PD
[29] K. Vichienchom, W. Liu, Analysis of phase noise due to bang-bang phase detector in LL-based clock and data recovery circuits, Proc. ISCAS 2003, vol. 1, pp. 617-620, May 2003
[30] Lee T H,Bulzacchelli J F.A 155 MHz clock recovery delay and phaselocked loop[J].IEEE Journal on Solid state Circuits,1992,27(12)
[31] J. D. H. Alexander,,Clock Recovery from Random Binary Data, Electronics Letters, vol. 11, pp.541-542, Oct. 1975
[32] M. Ramezani and C. A. T. Salama,A 10GbIs CDR with a Half-rate Bang-Bang Phase Detector,ISCAS, Proceedings, vo1.2, pp. 181-184, May 2003
[33] 13]All Hajimir,Thomas H Lee,Jitter and Phase Noise in Ring Oscillators,IEEE JSSC,VoI.34,PP.790-804,June 1999
[34] Taesung Kim,Beomsup Kim.Phase Interpolator Using Delay Locked Loop [C] SSMSD 2003
[35]陈莹梅,王志功,熊明珍等. 2.5Gb/s单片时钟恢复数据判决与1:4分接集成电路的设计.半导体学报,2005,26(8):
[36]唐世民. PCI Express中的2.5Gbps时钟数据恢复电路的设计与实现.国防科技大学硕士论文,2006年
[37]射频集成电路与系统李智群等著科学出版社2008.8
[38] Behzad Razavi著,陈贵灿等译.模拟集成电路设计.西安交通大学出版社,2002.12
[39] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic著,周润德译.数字集成电路电路系统与设计(第二版).电子工业出版社, 2006.08
[40]李学初,高清运,陈浩琼.高性能数字时钟恢复电路.固体电子学研究与进展. Vol.28,No.3 Sep,2008
[41] Alan Hastings,模拟电路版图艺术[M],王志功译,清华大学出版社,2007.9
[2] RapidIO嵌入式系统互连总线概述.http://www.rte-sky.com
[3] Serial RapidIO 2.1 IP Core. http://www.lattice.com
[4] Mehrdad Ramezani. Gigabit per second Clock and Data Recovery Circuits for Local Area Networks University of Toronto, 2004
[5] Jafar Savoj. A 10-Gb/s CMOS Clock and Data Recovery Circuit University of California, Los Angeles, 2001
[6] Jun Cao. Clock Multiplier Unit and Clock Data Recovery Circuit for 10Gb/s Broadband Communication in 0.18μm CMOS, Irvine 2003
[7] RapidIO Technology White Paper. http://www.rapidio.org
[8]裴济杰. RapidIO成就高速互连之美. 2005
[9] Sam Fuller等著,王勇等译. RapidIO嵌入式系统互连.北京:电子工业出版社, 2006.6
[10] RapidIO Trade Association. RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 2.1, 2009.08
[11] Cattalen, Pelard, et al. Realization of multi-gigabit channel equalization and crosstalk cancellation integrated circuits. IEEE Journal of Solid-State Circuits, 2004,39(10):1659-1669
[12] J. Caroselli, C. Liu. An Analytic System Model for High-Speed Interconnects and its Application to the Specification of Signaling and Equalization Architectures for 10Gbps Backplane Communication. IEC DesignCon 2006, 2006.01
[13] Kreien K. Iniewski, R. Badalone, M. Lapointe, M. Syrzycki. SERDES Technology for Gigabit I/O Communications in Storage Area Networking. IWSOC'04 IEEE, 2004
[14] Dengpeng Chen, Zhongxiang Shen. Bi-directional coupling between two coupled transmission lines. IEEE Microwave and Wireless Components Letters, 2003,13(12):514-516
[15] kamp.R,Langmann.U,Zimmermann.C. A 10Gb/s CMOS Clock and Data Recovery Circuit with all Analog Phase Interpolator[J].IEEE Journal of Solid State Circuits,2005,40,(3)
[16] B.Razavi,Challenges in the Design of High-Speed Clock Data Recovery Circuit IEEE
[17] Chin-Sheng Chen, Chang,R.C.A new prescaler for fully integrated 5-GHz MOS frequency synthesizer Circuits and Systems, 2004. ISCAS '04. Proce of the 2004 International Symposium on ,Volume: 4, May 2004 , 23-26
[18] S.Sidiropoulos. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers. IEEE Symp.VLSI Circuits, 2003:185-188
[19] A CMOS mixed signal clock and data recovery circuit for PCEI 6G backplane transceiver.IEEE J Solid State Cireuits,2006,41:597
[20] Wang Huan,Wang Zhigong,Feng Jun,Xiong Mingzhen,Zhang Li.2.488 Gbit/s clock and data recovery circuit in 0.35um CMOS in Joumal of southeast University,2006,pp 143-147.
[21] Hyung-Wook Jang , Sung-Sop Lee, Jin-Ku Kang A Clock Recovery Circuit using Half-rate 4X oversampling PD
[22] Phase Interpolator Based CDR, http://www.rambus.com
[23] S. I. Ahmed Tad A. Kwasniewski ,Overview of oversampling clock and data recovery circuits
[24] Cheng, et al.A Fast-Lock DLL with Power-On Reset Circuit, IEICE Trans on Fundamentals, Vol.E87-A No.9, pp.2210-2220, Sep. 2004.
[25] Saleem Mukhtar.Interval Modulation:A New Paradigm for the Design of Hish Speed Communication Systems [Z].Pasadena:California Institute of Technology,2004
[26] Behzad Razavi,Challenges in the Design of High-Speed Clock and Data Recovery Circuits, IEEE Communication Magazine,vol.40,Aug.2002, pp.94-101
[27] Lu Ping,Ye Fan and Ren Junyan,A Low-Jitter Frequency Synthesizer with Dynamic PhaseInterpolation for High-Speed Ethemet,IEEE,2006
[28] Hyung-Wook Jang , Sung-Sop Lee, Jin-Ku Kang. A Clock Recovery Circuit using Half-rate 4X oversampling PD
[29] K. Vichienchom, W. Liu, Analysis of phase noise due to bang-bang phase detector in LL-based clock and data recovery circuits, Proc. ISCAS 2003, vol. 1, pp. 617-620, May 2003
[30] Lee T H,Bulzacchelli J F.A 155 MHz clock recovery delay and phaselocked loop[J].IEEE Journal on Solid state Circuits,1992,27(12)
[31] J. D. H. Alexander,,Clock Recovery from Random Binary Data, Electronics Letters, vol. 11, pp.541-542, Oct. 1975
[32] M. Ramezani and C. A. T. Salama,A 10GbIs CDR with a Half-rate Bang-Bang Phase Detector,ISCAS, Proceedings, vo1.2, pp. 181-184, May 2003
[33] 13]All Hajimir,Thomas H Lee,Jitter and Phase Noise in Ring Oscillators,IEEE JSSC,VoI.34,PP.790-804,June 1999
[34] Taesung Kim,Beomsup Kim.Phase Interpolator Using Delay Locked Loop [C] SSMSD 2003
[35]陈莹梅,王志功,熊明珍等. 2.5Gb/s单片时钟恢复数据判决与1:4分接集成电路的设计.半导体学报,2005,26(8):
[36]唐世民. PCI Express中的2.5Gbps时钟数据恢复电路的设计与实现.国防科技大学硕士论文,2006年
[37]射频集成电路与系统李智群等著科学出版社2008.8
[38] Behzad Razavi著,陈贵灿等译.模拟集成电路设计.西安交通大学出版社,2002.12
[39] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic著,周润德译.数字集成电路电路系统与设计(第二版).电子工业出版社, 2006.08
[40]李学初,高清运,陈浩琼.高性能数字时钟恢复电路.固体电子学研究与进展. Vol.28,No.3 Sep,2008
[41] Alan Hastings,模拟电路版图艺术[M],王志功译,清华大学出版社,2007.9