SOPC芯片FDP2009设计验证以及芯片可重构应用研究
|
摘要
近些年来,可配置硬件由于灵活性和费用低等优点表现出明显强于ASIC的发展势头。但可配置硬件固有的弱点如功耗高、速度慢、资源冗余等使其在面对复杂功能设计的要求时还是会感到吃力,因此人们开始考虑通过技术上的融合在ASIC与可重配置硬件之间寻找一条中间道路——可编程片上系统SOPC。SOPC将FPGA与ASIC技术相融合,不仅可以降低开发SOC芯片的风险,缩短上市时间,而且其可重构的灵活能力提供了将同一芯片用到不同应用中去的机会,尤其适用于不断变化和发展标准的产品开发中,例如通讯和网络芯片产品等。
动态可重构是指在系统运行过程中可重配置部分能够被重复配置,在不同的时刻完成不同的功能。和静态可重构相比,动态可重构可以更充分的利用可重配置硬件。动态可重构技术是国际上研究的热点,尤其是在可重配置计算方面。本文主要从可重配置SOPC研究领域的三个主要方面(硬件、软件和应用)出发,对目前的可重构SOPC研究工作做出总结。本文所做的工作与创新点如下：
1.参与SOPC系统的架构设计,协助确定了整体架构与设计目标。SOPC系统中的EBI控制器设计,完成各个模块的集成工作。
2. SOPC系统设计中的验证环境建立以及各个模块的验证工作,建立了软硬件协同仿真环境。完成了SOPC系统芯片的后仿真与形式验证工作。在本文中我们提出了适合于SOPC设计的自主设计的自动化回归验证系统,使在同等95%验证覆盖率条件下,验证时间缩短了约30%。
3. SOPC软件系统设计。初始化程序设计,并编写了UART通信、FPGA通信的驱动程序。并且参与了FDP2009芯片的测试工作。
4.共同提出了基于自主设计FPGA和新的总线宏结构,并在此基础上实现了部分重配置实例。
5.基于FPGA的可重配置系统应用研究,基于FDP300K的可重配置滤波器设计。利用自主设计的总线宏,完成了部分重配置的实现。经过测试,发现可重配置滤波器设计具有配置快速和图像效果好的特点。
In recent years, reconfigurable devices are developing fast because of its flexibility and less development cost. But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations. So people began to consider combination of ASIC and reconfigurable device on a single chip, which is SOPC. SOPC can not only decrease development risk and timing to market, but also be used in different applications, especially of products that keep varying, for example, communication and network products.
Dynamically reconfiguration means reconfigurable device of the chip can be reconfigured repeatable, and performs different functions at different times. Compared with static reconfiguration, dynamic reconfiguration can use the reconfigurable device more thoroughly. It's a hot spot of research in the world, especially in reconfigurable computing.
This paper mainly concludes my research work in reconfigurable SOPC in 3 major parts:hardware, software and application. The following works and innovations are completed:
1. SOPC hardware system architecture design and discussion. Helps to define the system architecture and design goals. The design of EBI controller which is used in the SOPC. The integration of the blocks in the system.
2. The building-up of the SOPC system-level verification and block-level verification environment. The set-up of the hardware-software co-simulation environment. The post-layout simulation and formal verification tasks. We propose an innovative automated regression system. The system helps to achieve the same simulation coverage (95%) and the total simulation time is reduced by approximately 30%.
3. SOPC software design, including the OS kernel porting, drivers design and application design. The design of the PowerPC initialization program and UART, FPGA communication driver programs. Writing the test-cases which are specialized for the system verification and hardware testing.
4. Being the co-designer of the novel bus macro based on the FDP FPGA. And we realize the whole reconfigurable system based on this bus macro.
5. The reconfigurable application research based on FPGA. The reconfigurable image filter designed implemented on FDP300K FPGA device. Using self-design FPGA internal bus macro to implement the partial reconfigurable system. The test results showed that the reconfigurable filter has the feature of fast configuration speed and good output image quality.
动态可重构是指在系统运行过程中可重配置部分能够被重复配置,在不同的时刻完成不同的功能。和静态可重构相比,动态可重构可以更充分的利用可重配置硬件。动态可重构技术是国际上研究的热点,尤其是在可重配置计算方面。本文主要从可重配置SOPC研究领域的三个主要方面(硬件、软件和应用)出发,对目前的可重构SOPC研究工作做出总结。本文所做的工作与创新点如下：
1.参与SOPC系统的架构设计,协助确定了整体架构与设计目标。SOPC系统中的EBI控制器设计,完成各个模块的集成工作。
2. SOPC系统设计中的验证环境建立以及各个模块的验证工作,建立了软硬件协同仿真环境。完成了SOPC系统芯片的后仿真与形式验证工作。在本文中我们提出了适合于SOPC设计的自主设计的自动化回归验证系统,使在同等95%验证覆盖率条件下,验证时间缩短了约30%。
3. SOPC软件系统设计。初始化程序设计,并编写了UART通信、FPGA通信的驱动程序。并且参与了FDP2009芯片的测试工作。
4.共同提出了基于自主设计FPGA和新的总线宏结构,并在此基础上实现了部分重配置实例。
5.基于FPGA的可重配置系统应用研究,基于FDP300K的可重配置滤波器设计。利用自主设计的总线宏,完成了部分重配置的实现。经过测试,发现可重配置滤波器设计具有配置快速和图像效果好的特点。
In recent years, reconfigurable devices are developing fast because of its flexibility and less development cost. But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations. So people began to consider combination of ASIC and reconfigurable device on a single chip, which is SOPC. SOPC can not only decrease development risk and timing to market, but also be used in different applications, especially of products that keep varying, for example, communication and network products.
Dynamically reconfiguration means reconfigurable device of the chip can be reconfigured repeatable, and performs different functions at different times. Compared with static reconfiguration, dynamic reconfiguration can use the reconfigurable device more thoroughly. It's a hot spot of research in the world, especially in reconfigurable computing.
This paper mainly concludes my research work in reconfigurable SOPC in 3 major parts:hardware, software and application. The following works and innovations are completed:
1. SOPC hardware system architecture design and discussion. Helps to define the system architecture and design goals. The design of EBI controller which is used in the SOPC. The integration of the blocks in the system.
2. The building-up of the SOPC system-level verification and block-level verification environment. The set-up of the hardware-software co-simulation environment. The post-layout simulation and formal verification tasks. We propose an innovative automated regression system. The system helps to achieve the same simulation coverage (95%) and the total simulation time is reduced by approximately 30%.
3. SOPC software design, including the OS kernel porting, drivers design and application design. The design of the PowerPC initialization program and UART, FPGA communication driver programs. Writing the test-cases which are specialized for the system verification and hardware testing.
4. Being the co-designer of the novel bus macro based on the FDP FPGA. And we realize the whole reconfigurable system based on this bus macro.
5. The reconfigurable application research based on FPGA. The reconfigurable image filter designed implemented on FDP300K FPGA device. Using self-design FPGA internal bus macro to implement the partial reconfigurable system. The test results showed that the reconfigurable filter has the feature of fast configuration speed and good output image quality.
引文
[1]http://www.smte.net/Get/Docs/Ele/2008-1/14/1001140510131101316673 2836.htm
[2]S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol.86, No.4, pp.615-638, April,1998
[3]Vassiliadis, Stamatis; Soudris, Dimitrios (Eds.). "Fine-and Coarse-Grain Reconfigurable Computing.2007", XVI,384 p. ISBN: 978-1-4020-6504-0
[4]http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/stxiv-inde x.jsp
[5]"Virtex-6 Family Overview", Xilinx Inc., DS150 (v2.2) January 28,2010
[6]Brown S, Francis R, Rose J, et al. Field-programmable gate arrays [M] Norwell:Kluwer,1992.
[7]http://brass.cs.berkeley.edu/
[8]http://brass.cs.berkeley.edu/SCORE/
[9]http://www.eecg.toronto.edu/～jece/OneChip/
[10]http://www.ed-china.com/ART_8800027417_400014_500013_HP_da4a 4438.HTM
[11]Llamocca, D.; Pattichis, M.; Vera, G.A., "A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters", Reconfigurable Computing and FPGAs,2009. ReConFig'09. International Conference on. Publication Year:2009, Page(s):332-337
[12]Choi, Chang-Seok; Lee, Hanho, "A Partial Self-Reconfigurable Adaptive FIR Filter System" Signal Processing Systems,2007 IEEE Workshop on Digital Object, Publication Year:2007, Page(s):204-209
[13]Srivastava, N.; Trahan, J.L.; Vaidyanathan, R.; Rai, S., "Adaptive image filtering using run-time reconfiguration", International Parallel and Distributed Processing Symposium,2003. Proceedings., Publication Year:2003
[14]IBM Microelectronics Corp., "CoreConnect Bus Architecture". http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/crcon_pb.pdf
[15]David P.Schultz; Lawrence C.Hung. E.Erich Goetting. Method and Structure of Configuring FPGAs. [P/OL] US.Patent.Ser.No.6,204,687 B1.Mar 20,2001
[16]Xie Jing, Wang Yabin, Lai Jinmei, Tong Jiarong, "Fast Configuration Architecture of FPGA Suitable For Bitstream Compression" The International Conference on ASIC. ASICON 2009.vol.PP, Forthcoming, Oct 2009, pp.1-1
[17]Mansour H.Assaf, Sunil R.Das, Wael Hermas, Emil M.Petriu, Satyendra Biswas "Verification of Ethernet IP Core MAC Design Using Deterministic Test Methodology", IEEE International Instrumentation and Measurement Technology Conference Victoria, Vancouver Island, Canada, May 12-15,2008
[18]J. Bergeron, Writing Testbenches:Functional Verification of HDL Models. New York:Springer 2003
[19]IS61WV512 Datasheet, Integrated Silicon Solution, Inc., Jun.2008
[20]Developing PowerPC Embedded Application Binary Interface (EABI) Compliant Programs, Microcontroller Applications, IBM Microelectronics Research Triangle Park, NC, September 21,1998
[21]Yang Huaqiu, Lai Jinmei, Patent:"A bus macro structure based-on vertical FPGA CLB architecture used in dynamic partial reconfigurable designs",2009
[22]PowerPC 405 Embedded Processor Core User's Manual, Fifth Edition (December 2001), IBM Microelectronics Corporation
[23]IBM Microelectronics, RISCWatchDebugger for PowerPC Processors, International Business Machines Corporation 2008
[24]Jun Ohta (2008). Smart CMOS Image Sensors and Applications. CRC Press. ISBN 0849336813
[25]Lindsay MacDonald (2006). Digital Heritage. Butterworth-Heinemann. ISBN 0750661836.
[26]Junichi Nakamura (2005). Image Sensors and Signal Processing for Digital Still Cameras. CRC Press. ISBN 0849335450.
[27]Rafael C. Gonzalez, Richard E. Woods (2007). Digital Image Processing. Pearson Prenctice Hall. ISBN 013168728X.
[28]Linda G. Shapiro and George C. Stockman (2001). Computer Vision. Prentice-Hall. ISBN 0130307963.
[29]Charles Boncelet (2005). "Image Noise Models". in Alan C. Bovik. Handbook of Image and Video Processing. Academic Press. ISBN 0121197921.
[30]Robert A. Schowengerdt, Remote Sensing, Third Edition:Models and Methods for Image Processing
[31]Llamocca, D.; Pattichis, M.; Vera, G.A., "A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters", Reconfigurable Computing and FPGAs,2009. ReConFig'09. International Conference on. Publication Year:2009, Page(s):332-337
[32]Choi, Chang-Seok; Lee, Hanho, "A Partial Self-Reconfigurable Adaptive FIR Filter System" Signal Processing Systems,2007 IEEE Workshop on Digital Object, Publication Year:2007, Page(s):204-209
[33]Srivastava, N.; Trahan, J.L.; Vaidyanathan, R.; Rai, S., "Adaptive image filtering using run-time reconfiguration", International Parallel and Distributed Processing Symposium,2003. Proceedings., Publication Year:2003
[34]K.Aiswarya et al., A NEW AND EFFICIENT ALGORITHM FOR THE REMOVAL OF HIGH DENSITY SALT AND PEPPER NOISE IN IMAGES AND VIDEOS,2010 Second International Conference on Computer Modeling and Simulation
[35]Ying Zhang, Xuebo Chen, A New Method of Image Noises Removal, Proceedings of the 7th World Congress on Intelligent Control and Automation
[36]Cheng-Hsiung Hsieh and Po-Chin Huang, Adaptive Rank Order Filter for Image Noise Removal,2009 World Congress on Computer Science and Information Engineering
[37]Chandra Sekhar Panda, Srikanta Patnaik, "Filtering and Performance Evaluation for Restoration of Grayscale Image Corrupted by Salt & Pepper Noise Using Low Pass Filtering Schemes", Second International Conference on Emerging Trends in Engineering and Technology, ICETET-09
[38]J.F. Cai, R.H. Chan, and M. Nikolova. Two-Phase Methods for Deblurring Images Corrupted by Impulse Plus Gaussian Noise. AIMS Journal on Inverse Problems and Imaging,2(2):187-204,2008.
[39]Katarina Paulsson, Michael Hubner, Salih Bayar, and Jurgen Becker. Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan Ⅲ-based Systems. ReCoSoc2007, Montpellier, France, June 2007.
[40]K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, and J. Becker. "Implementation of a Virtual Internal Configuration Access Port (JCAP) for enabling Partial Self-Reconfiguration on Xilinx Spartan-Ⅲ FPGAs". FPL, Amsterdam, Netherland, August 2007.
[41]Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch "RUN-TIME PARTIAL RECONFIGURATION SPEED INVESTIGATION AND ARCHITECTURAL DESIGN SPACE EXPLORATION", FPL 2009
[2]S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol.86, No.4, pp.615-638, April,1998
[3]Vassiliadis, Stamatis; Soudris, Dimitrios (Eds.). "Fine-and Coarse-Grain Reconfigurable Computing.2007", XVI,384 p. ISBN: 978-1-4020-6504-0
[4]http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/stxiv-inde x.jsp
[5]"Virtex-6 Family Overview", Xilinx Inc., DS150 (v2.2) January 28,2010
[6]Brown S, Francis R, Rose J, et al. Field-programmable gate arrays [M] Norwell:Kluwer,1992.
[7]http://brass.cs.berkeley.edu/
[8]http://brass.cs.berkeley.edu/SCORE/
[9]http://www.eecg.toronto.edu/～jece/OneChip/
[10]http://www.ed-china.com/ART_8800027417_400014_500013_HP_da4a 4438.HTM
[11]Llamocca, D.; Pattichis, M.; Vera, G.A., "A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters", Reconfigurable Computing and FPGAs,2009. ReConFig'09. International Conference on. Publication Year:2009, Page(s):332-337
[12]Choi, Chang-Seok; Lee, Hanho, "A Partial Self-Reconfigurable Adaptive FIR Filter System" Signal Processing Systems,2007 IEEE Workshop on Digital Object, Publication Year:2007, Page(s):204-209
[13]Srivastava, N.; Trahan, J.L.; Vaidyanathan, R.; Rai, S., "Adaptive image filtering using run-time reconfiguration", International Parallel and Distributed Processing Symposium,2003. Proceedings., Publication Year:2003
[14]IBM Microelectronics Corp., "CoreConnect Bus Architecture". http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/crcon_pb.pdf
[15]David P.Schultz; Lawrence C.Hung. E.Erich Goetting. Method and Structure of Configuring FPGAs. [P/OL] US.Patent.Ser.No.6,204,687 B1.Mar 20,2001
[16]Xie Jing, Wang Yabin, Lai Jinmei, Tong Jiarong, "Fast Configuration Architecture of FPGA Suitable For Bitstream Compression" The International Conference on ASIC. ASICON 2009.vol.PP, Forthcoming, Oct 2009, pp.1-1
[17]Mansour H.Assaf, Sunil R.Das, Wael Hermas, Emil M.Petriu, Satyendra Biswas "Verification of Ethernet IP Core MAC Design Using Deterministic Test Methodology", IEEE International Instrumentation and Measurement Technology Conference Victoria, Vancouver Island, Canada, May 12-15,2008
[18]J. Bergeron, Writing Testbenches:Functional Verification of HDL Models. New York:Springer 2003
[19]IS61WV512 Datasheet, Integrated Silicon Solution, Inc., Jun.2008
[20]Developing PowerPC Embedded Application Binary Interface (EABI) Compliant Programs, Microcontroller Applications, IBM Microelectronics Research Triangle Park, NC, September 21,1998
[21]Yang Huaqiu, Lai Jinmei, Patent:"A bus macro structure based-on vertical FPGA CLB architecture used in dynamic partial reconfigurable designs",2009
[22]PowerPC 405 Embedded Processor Core User's Manual, Fifth Edition (December 2001), IBM Microelectronics Corporation
[23]IBM Microelectronics, RISCWatchDebugger for PowerPC Processors, International Business Machines Corporation 2008
[24]Jun Ohta (2008). Smart CMOS Image Sensors and Applications. CRC Press. ISBN 0849336813
[25]Lindsay MacDonald (2006). Digital Heritage. Butterworth-Heinemann. ISBN 0750661836.
[26]Junichi Nakamura (2005). Image Sensors and Signal Processing for Digital Still Cameras. CRC Press. ISBN 0849335450.
[27]Rafael C. Gonzalez, Richard E. Woods (2007). Digital Image Processing. Pearson Prenctice Hall. ISBN 013168728X.
[28]Linda G. Shapiro and George C. Stockman (2001). Computer Vision. Prentice-Hall. ISBN 0130307963.
[29]Charles Boncelet (2005). "Image Noise Models". in Alan C. Bovik. Handbook of Image and Video Processing. Academic Press. ISBN 0121197921.
[30]Robert A. Schowengerdt, Remote Sensing, Third Edition:Models and Methods for Image Processing
[31]Llamocca, D.; Pattichis, M.; Vera, G.A., "A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters", Reconfigurable Computing and FPGAs,2009. ReConFig'09. International Conference on. Publication Year:2009, Page(s):332-337
[32]Choi, Chang-Seok; Lee, Hanho, "A Partial Self-Reconfigurable Adaptive FIR Filter System" Signal Processing Systems,2007 IEEE Workshop on Digital Object, Publication Year:2007, Page(s):204-209
[33]Srivastava, N.; Trahan, J.L.; Vaidyanathan, R.; Rai, S., "Adaptive image filtering using run-time reconfiguration", International Parallel and Distributed Processing Symposium,2003. Proceedings., Publication Year:2003
[34]K.Aiswarya et al., A NEW AND EFFICIENT ALGORITHM FOR THE REMOVAL OF HIGH DENSITY SALT AND PEPPER NOISE IN IMAGES AND VIDEOS,2010 Second International Conference on Computer Modeling and Simulation
[35]Ying Zhang, Xuebo Chen, A New Method of Image Noises Removal, Proceedings of the 7th World Congress on Intelligent Control and Automation
[36]Cheng-Hsiung Hsieh and Po-Chin Huang, Adaptive Rank Order Filter for Image Noise Removal,2009 World Congress on Computer Science and Information Engineering
[37]Chandra Sekhar Panda, Srikanta Patnaik, "Filtering and Performance Evaluation for Restoration of Grayscale Image Corrupted by Salt & Pepper Noise Using Low Pass Filtering Schemes", Second International Conference on Emerging Trends in Engineering and Technology, ICETET-09
[38]J.F. Cai, R.H. Chan, and M. Nikolova. Two-Phase Methods for Deblurring Images Corrupted by Impulse Plus Gaussian Noise. AIMS Journal on Inverse Problems and Imaging,2(2):187-204,2008.
[39]Katarina Paulsson, Michael Hubner, Salih Bayar, and Jurgen Becker. Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan Ⅲ-based Systems. ReCoSoc2007, Montpellier, France, June 2007.
[40]K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, and J. Becker. "Implementation of a Virtual Internal Configuration Access Port (JCAP) for enabling Partial Self-Reconfiguration on Xilinx Spartan-Ⅲ FPGAs". FPL, Amsterdam, Netherland, August 2007.
[41]Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch "RUN-TIME PARTIAL RECONFIGURATION SPEED INVESTIGATION AND ARCHITECTURAL DESIGN SPACE EXPLORATION", FPL 2009