地震勘探数字滤波芯片CS5376与FPGA的接口设计
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摘要
该文阐述了高度集成的地震信号采集单元的工作原理,重点研究采集单元主控制器——现场可编程门阵列(FPGA)和地震信号滤波芯片CS5376的接口设计。介绍2种数据接口方案:FPGA的串行外设接口(SPI)分时复用,即同时用作命令通道和数据通道;基于FPGA硬件逻辑用VHDL语言自行设计的专用串行数据接口(SD口)。测试表明,这2种方案都能实现FPGA和CS5376之间可靠的数据传输,自行设计的SD接口具有更高的数据传输率,但是结构比较复杂。
This paper describes a highly integrated seismic signal acquisition unit with a focus on the design of the interface between the main controller FPGA(field programmable gate array)and the seismic signal filter chip CS5376.In one design,the serial peripheral interface of the FPGA is timeshared and is not only used as the order transfer channel but also as the data transfer channel.The other design uses a special SD data transfer interface based on the FPGA hardware logic and the VHDL language.Tests show that these two methods can both realize reliable data transfer between the FPGA and the CS5376.The transfer rate for the SD interface is faster,but the structure is more complicated.
This paper describes a highly integrated seismic signal acquisition unit with a focus on the design of the interface between the main controller FPGA(field programmable gate array)and the seismic signal filter chip CS5376.In one design,the serial peripheral interface of the FPGA is timeshared and is not only used as the order transfer channel but also as the data transfer channel.The other design uses a special SD data transfer interface based on the FPGA hardware logic and the VHDL language.Tests show that these two methods can both realize reliable data transfer between the FPGA and the CS5376.The transfer rate for the SD interface is faster,but the structure is more complicated.
引文
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[2]Cirrus Logic Corp.CS5376datasheet[R].Cirrus Logic,2005.
[3]李兰英.Nios II嵌入式软核SOPC设计原理及应用[M].北京:北京航空航天大学出版社,2006.
[4]高枫,王玉松.基于NiosII自定制Avalon设备的设计与实现[J].中国测试技术,2007,33(4):105-108.GAO Feng,WANG Yusong.Design and implementation of user defined Avalon device on NiosII[J].China Measurement&Testing Technology,2007,33(4):105-108.(in Chinese)
[5]Altera Corp.Single-and Dual-Clock FIFO Megafunction User Guide[R].Altera,2005.
[6]张维旭,贺占庄.基于FPGA的异步FIFO设计[J].计算机技术与发展,2006,16(7):168-170.ZHANG Weixu,HE Zhanzhuang.Asynchronous FIFO design based on FPGA[J].Computer Technology and Development,2006,16(7):168-170.(in Chinese)
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