支持SMT的微结构模拟器实现与应用
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摘要
某国产处理器微结构模拟器(MASim)无法支持同时多线程(SMT)技术,难以满足研究与工程需求。为此,提出一种新的微结构模拟器。将MASim和SMT技术相结合,从架构模拟、仿真速度、仿真精度与灵活可控等方面采用模块化和队列优化等技术进行设计与实现。实验结果表明,该模拟器的仿真精度、仿真速度与原有的单线程微结构模拟器基本相当,SMT技术对该系列国产处理器具有性能提升作用,每时钟周期执行指令数平均提升29.61%。
A domestic processor Micro Architecture Simulator(MASim) cannot support Simultaneous Multithreading(SMT) technology.It is difficult to meet the research and engineering requirements.Therefore,a new micro architecture simulator is proposed.The combination of MASim and SMT technology is adopted to design and realize the technology of modularization and queue optimization from the aspects of architecture simulation,simulation speed,simulation precision and flexible controllability.Experimental results show that the simulation accuracy and the simulation speed are almost the same as those of the original single-thread micro architecture simulator.SMT technology has the function of enhancing the performance of the series of domestic processors.The number of Instructions Per Clock Cycle(IPC) is increased by an average of 29.61%.
A domestic processor Micro Architecture Simulator(MASim) cannot support Simultaneous Multithreading(SMT) technology.It is difficult to meet the research and engineering requirements.Therefore,a new micro architecture simulator is proposed.The combination of MASim and SMT technology is adopted to design and realize the technology of modularization and queue optimization from the aspects of architecture simulation,simulation speed,simulation precision and flexible controllability.Experimental results show that the simulation accuracy and the simulation speed are almost the same as those of the original single-thread micro architecture simulator.SMT technology has the function of enhancing the performance of the series of domestic processors.The number of Instructions Per Clock Cycle(IPC) is increased by an average of 29.61%.
引文
[1]Cristiano P.Reproducible User-level Simulation of Multithreaded Workloads[D].San Diego,USA:University of California,2007.
[2]Kenneth C B.Summarizing Multiprocessor Program Execution with Versatile,Microarchitecture-independent Snapshots[D].Cambridge,USA:Massachusetts Institute Technology,2006.
[3]Austin T,Larson E,Ernst D.SimpleS calar:An Infra-structure for Computer System Modeling[J].Computer,2002,35(2):59-67.
[4]Binkert N,Beckmann B,Black G,et al.The GEM5Simulator[J].ACM SIGARCH Computer Architecture News,2011,39(2):1-7.
[5]Engblom J,Ekblom D.SIMICS:A Commercially Proven Full-system Simulation Framework[EB/OL].(2015-12-06).http://engbloms.se/publications/engblomsesp2006.pdf.
[6]张福新,章隆兵,胡伟武.基于SimpleS calar的龙芯CPU模拟器Sim-Godson[J].计算机学报,2007,30(1):68-73.
[7]高翔,张福新,汤彦,等.基于龙芯CPU的多核全系统模拟器SimO S-Goodson[J].软件学报,2007,18(4):1047-1055.
[8]Tullsen D M,Eggers S J,Levy H M.Simultaneous Multithreading:Maximizing on-chip Parallelism[C]//Proceedings of the 22nd Annual International Sympo-sium on Computer Architecture.New York,USA:ACM Press,1998:533-544.
[9]Tullsen D M,Brown J A.Handling Long-latency Loads in a Simultaneous Multithreading Processor[C]//Proceedings of the 34 th Annual ACM/IEEE International Symposium on Microarchitecture.Washington D.C.,USA:IEEE Computer Society,2001:318-327.
[10]Eggers S J,Emer J S,Leby H M,et al.Simultaneous Multithreading:A Platform for Next-generation Pro-cessors[J].IEEE Micro,1997,17(5):12-19.
[11]Tullsen D M,Eggers S J,Emer J S,et al.Exploiting Choice:Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor[C]//Proceed-ings of ACM SIGARCH Computer Architecture News.New York,USA:ACM Press,1996:191-202.
[12]Lo J L,Emer J S,Levy H M,et al.Converting Threadlevel Parallelism to Instruction-level Parallelism via Simultaneous Multithreading[J].ACM Transactions on Computer Systems,1997,15(3):322-354.
[13]Henning J L.SPEC CPU2000:Measuring CPU Performance in the New Millennium[J].Computer,2000,33(7):28-35.
[14]Tullsen D M,Snavely A.Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor[J].ACM Sigmetrics Performance Evaluation Review,2002,30(1):66-76.
[15]Swanson S,McD owell L K,Swift M M,et al.An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors[J].ACM Transactions on Computer Systems,2003,21(3):314-340.
[16]Yi J J,Lilja D J.Simulation of Computer Architectures:Simulators,Benchmarks,Methodologies,and Recommendations[J].IEEE Transactions on Computers,2006,55(3):268-280.
[17]Sazeides Y,Juan T.How to Compare the Performance of Two SMT Microarchitectures[C]//Proceedings of IEEEInternational Symposium on Performance Analysis of Systems&Software.Washington D.C.,USA:IEEEPress,2001:180-183.
[2]Kenneth C B.Summarizing Multiprocessor Program Execution with Versatile,Microarchitecture-independent Snapshots[D].Cambridge,USA:Massachusetts Institute Technology,2006.
[3]Austin T,Larson E,Ernst D.SimpleS calar:An Infra-structure for Computer System Modeling[J].Computer,2002,35(2):59-67.
[4]Binkert N,Beckmann B,Black G,et al.The GEM5Simulator[J].ACM SIGARCH Computer Architecture News,2011,39(2):1-7.
[5]Engblom J,Ekblom D.SIMICS:A Commercially Proven Full-system Simulation Framework[EB/OL].(2015-12-06).http://engbloms.se/publications/engblomsesp2006.pdf.
[6]张福新,章隆兵,胡伟武.基于SimpleS calar的龙芯CPU模拟器Sim-Godson[J].计算机学报,2007,30(1):68-73.
[7]高翔,张福新,汤彦,等.基于龙芯CPU的多核全系统模拟器SimO S-Goodson[J].软件学报,2007,18(4):1047-1055.
[8]Tullsen D M,Eggers S J,Levy H M.Simultaneous Multithreading:Maximizing on-chip Parallelism[C]//Proceedings of the 22nd Annual International Sympo-sium on Computer Architecture.New York,USA:ACM Press,1998:533-544.
[9]Tullsen D M,Brown J A.Handling Long-latency Loads in a Simultaneous Multithreading Processor[C]//Proceedings of the 34 th Annual ACM/IEEE International Symposium on Microarchitecture.Washington D.C.,USA:IEEE Computer Society,2001:318-327.
[10]Eggers S J,Emer J S,Leby H M,et al.Simultaneous Multithreading:A Platform for Next-generation Pro-cessors[J].IEEE Micro,1997,17(5):12-19.
[11]Tullsen D M,Eggers S J,Emer J S,et al.Exploiting Choice:Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor[C]//Proceed-ings of ACM SIGARCH Computer Architecture News.New York,USA:ACM Press,1996:191-202.
[12]Lo J L,Emer J S,Levy H M,et al.Converting Threadlevel Parallelism to Instruction-level Parallelism via Simultaneous Multithreading[J].ACM Transactions on Computer Systems,1997,15(3):322-354.
[13]Henning J L.SPEC CPU2000:Measuring CPU Performance in the New Millennium[J].Computer,2000,33(7):28-35.
[14]Tullsen D M,Snavely A.Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor[J].ACM Sigmetrics Performance Evaluation Review,2002,30(1):66-76.
[15]Swanson S,McD owell L K,Swift M M,et al.An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors[J].ACM Transactions on Computer Systems,2003,21(3):314-340.
[16]Yi J J,Lilja D J.Simulation of Computer Architectures:Simulators,Benchmarks,Methodologies,and Recommendations[J].IEEE Transactions on Computers,2006,55(3):268-280.
[17]Sazeides Y,Juan T.How to Compare the Performance of Two SMT Microarchitectures[C]//Proceedings of IEEEInternational Symposium on Performance Analysis of Systems&Software.Washington D.C.,USA:IEEEPress,2001:180-183.