嵌入式GPU中二级高速缓存的设计与实现
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摘要
针对嵌入式GPU与主存之间进行数据交互时出现速度不匹配的问题,设计了一种适用于嵌入式GPU的二级高速缓存Cache控制器.二级Cache控制器采用四路组相联的映射结构,使用伪最近最少使用(Pseudo_LRU)替换算法,可以管理16~512kB的二级高速缓存.实验结果表明,当选取Cache大小为128kB时,Cache的命中率达到71.12%.
A suitable for embedded GPU cache controller is designed for the speed mismatch problems data interaction between main memory and embedded GPU.The cache controller adopts a four-way set associative mapping structure,uses pseudo-Least Recently Used replacement algorithm.The size of CacheSRAM can be configured,which configuration range is 32~512 kB.The experimental results show that when the CacheSRAM capacity is 128 kB,hit rate of the graphics application's Cache can reach to 71.12%,the cache controller can further enhance the overall performance of embedded GPU.
A suitable for embedded GPU cache controller is designed for the speed mismatch problems data interaction between main memory and embedded GPU.The cache controller adopts a four-way set associative mapping structure,uses pseudo-Least Recently Used replacement algorithm.The size of CacheSRAM can be configured,which configuration range is 32~512 kB.The experimental results show that when the CacheSRAM capacity is 128 kB,hit rate of the graphics application's Cache can reach to 71.12%,the cache controller can further enhance the overall performance of embedded GPU.
引文
[1]史鸿声.可信嵌入式3D图形系统关键技术的研究[D].合肥:中国科学技术大学,2008.
[2]雷宇.移动设备上基于图像的图形绘制系统若干关键技术的研究[D].杭州:浙江大学,2005.
[3]张绪冰.基于高性能VIM体系结构的嵌入式存储系统的研究与实现[D].长沙:国防科学技术大学,2004.
[4]Steve Furber.ARM SoC体系结构[M].北京:北京航空航天大学出版社,2002.
[5]王思瑶,樊晓桠,肖楠.一种微处理器二级Cache的优化设计[J].科学技术与工程,2008,7(9):2356-2359.
[6]温泉.16位高性能CPU的Cache设计[D].中国地质大学(北京),2014.
[7]隋秀峰,吴俊敏,陈国良.同时多线程处理器上的Cache性能分析与优化[J].小型微型计算机系统,2009,30(1):159-163.
[8]J Hennessy,DPatterson.ComputerArchitecture:A Quantitative Approach[M].3rd ed.SanFrancisco:Morgan Kaufmann Publishers,2003.
[9]Jeong J,Dubios M.Cost-Sensitive Cache Replacement Algorithms[C]//The Ninth International Symposium on High-Performance Computer Architecture(HPCA-9'03).New Orleans,USA,2002.
[10]Ghasemzadeh H,Mazrouee S S,Kakoee M R.Modified Pseudo LRU Replacement Algorithm[C]//IEEE International Symposium and Workshop on Engineering of Computer Based Systems.China,IEEE Xplore,2006:6.
[2]雷宇.移动设备上基于图像的图形绘制系统若干关键技术的研究[D].杭州:浙江大学,2005.
[3]张绪冰.基于高性能VIM体系结构的嵌入式存储系统的研究与实现[D].长沙:国防科学技术大学,2004.
[4]Steve Furber.ARM SoC体系结构[M].北京:北京航空航天大学出版社,2002.
[5]王思瑶,樊晓桠,肖楠.一种微处理器二级Cache的优化设计[J].科学技术与工程,2008,7(9):2356-2359.
[6]温泉.16位高性能CPU的Cache设计[D].中国地质大学(北京),2014.
[7]隋秀峰,吴俊敏,陈国良.同时多线程处理器上的Cache性能分析与优化[J].小型微型计算机系统,2009,30(1):159-163.
[8]J Hennessy,DPatterson.ComputerArchitecture:A Quantitative Approach[M].3rd ed.SanFrancisco:Morgan Kaufmann Publishers,2003.
[9]Jeong J,Dubios M.Cost-Sensitive Cache Replacement Algorithms[C]//The Ninth International Symposium on High-Performance Computer Architecture(HPCA-9'03).New Orleans,USA,2002.
[10]Ghasemzadeh H,Mazrouee S S,Kakoee M R.Modified Pseudo LRU Replacement Algorithm[C]//IEEE International Symposium and Workshop on Engineering of Computer Based Systems.China,IEEE Xplore,2006:6.