基于细粒度的光片上网络MRR制程漂移容错研究
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  • 英文篇名:Study on fine-grain based fault tolerance of MRR process variation in photonic network on chip
  • 作者:朱爱军 ; 赵春霞 ; 胡聪 ; 许川佩 ; 李智
  • 英文作者:Zhu Aijun;Zhao Chunxia;Hu Cong;Xu Chuanpei;Li Zhi;School of Electronic Engineering and Automation,Guilin University of Electronic Technology;Guangxi Key Laboratory of Automatic Detecting Technology and Instruments;Guilin University of Aerospace Technology;
  • 关键词:制程漂移 ; 容错 ; 微环谐振器
  • 英文关键词:process variation;;fault tolerance;;microring resonator(MRR)
  • 中文刊名:YQXB
  • 英文刊名:Chinese Journal of Scientific Instrument
  • 机构:桂林电子科技大学电子工程与自动化学院;广西自动检测技术与仪器重点实验室;桂林航天工业学院;
  • 出版日期:2019-02-15
  • 出版单位:仪器仪表学报
  • 年:2019
  • 期:v.40
  • 基金:国家自然科学基金(61861012,61561012);; 广西自然科学基金联合资助培育项目(2018GXNSFAA138115);广西自然科学基金(2017GXNSFAA198021,2015GXNSFDA139030);; 广西自动检测技术与仪器重点实验室基金(YQ19101);; 广西中青年教师基础能力提升项目(2017KY0210)资助
  • 语种:中文;
  • 页:YQXB201902029
  • 页数:8
  • CN:02
  • ISSN:11-2179/TH
  • 分类号:252-259
摘要
光片上网络是片上网络发展的新方向,微环谐振器是光片上网络中的关键器件,然而由于微环谐振器对制程漂移较为敏感、极易发生故障,如何对制程漂移造成的微环谐振器故障进行容错是提高光片上网络可靠性的关键。针对该问题提出了一种细粒度的微环谐振器制程漂移容错方法,建立微环谐振器制程漂移模型,采用基于樽海鞘群算法的微环谐振器制程漂移容错方法,并结合多策略的冗余微环谐振器进行容错。实验结果证明,所提方法相比整数线性规划等方法,可以最高提高21%的带宽和减少66.7%的调整功耗,证明了所提方法的有效性。
        Photonic network-on-chip(PNoC) has been a new trend for next generation network-on-chip development. Microring resonator is the key component in PNoC. However, microring resonators are sensitive to process variation and prone to fault. Therefore, how to tolerant the microring resonator fault due to process variation is a key problem to improve the reliability of PNoC. Aiming at this problem, a fine-grain based tolerance method of microring resonator process variation is proposed. Firstly, the model of microring resonator process variation was built; then, a tolerance method of microring resonator process variation based on salp swarm algorithm was proposed; finally, the tolerance of a multi-strategy redundant microring resonator was conducted. The experiment results indicate that compared with integer linear programming method, the proposed approach increases the bandwidth by 21% and decreases the trimming power consumption by 66.7%, which proves the effectiveness of the proposed approach.
引文
[1] 胡聪,贾梦怡,许川佩,等. 基于时间Petri 网和THBA 的3D NoC 测试规划[J].仪器仪表学报, 2018, 39(1): 234- 242.HU C, JIA M Y, XU CH P, et al. Research on test planning of 3D NoC based on timed Petri net and THBA [J]. Chinese Journal of Scientific Instrument, 2018, 39(1): 234- 242.
    [2] 欧阳一鸣,胡立柱,安鑫,等. 无线片上网络高性能EMS容错方案设计 [J].仪器仪表学报, 2018, 39(5): 132-140.OUYANG Y M, HU L ZH, AN X, et al. High performance EMS fault tolerant scheme for wireless Network on chip [J]. Chinese Journal of Scientific Instrument, 2018, 39(5): 132-140.
    [3] 朱爱军,李智,许川佩. 三维堆叠SoC测试规划研究[J].电子测量与仪器学报, 2016, 30(1): 159-164.ZHU AI J, LI ZH, XU CH P. Test scheduling of three dimensional stacked SoC [J]. Journal of Electronic Measurement and Instrument, 2016, 30(1): 159-164.
    [4] ZHU AI J, XU CH P, LI ZH, et al. Hybridizing grey wolf optimization with differential evolution for global optimization and test scheduling for 3D stacked SoC [J]. Journal of Systems Engineering and Electronics, 2015, 26 (2): 317-328.
    [5] HU C, LI ZH, ZHOU T, et al. A multi-verse optimizer with levy flights for numerical optimization and its application in test scheduling for network-on-chip [J]. PloS one, 2016, 11(12):1- 22.
    [6] 朱爱军, 李智, 朱望纯,等.基于多目标差分进化的测试封装扫描设计 [J].仪表技术与传感器, 2014 (5):73-75.ZHU AI J, LI ZH, ZHU W CH, et al. Test wrapper design based on Multi-objective differential evolution [J]. Instrument Technique and Sensor, 2014 (5):73-75.
    [7] 朱爱军, 李智, 许川佩. 三维IP核测试封装扫描链多目标优化设计[J]. 电子测量与仪器学报, 2014, 28(4): 373-380.ZHU AI J, LI ZH, XU CH P. Three dimension test wrapper scan chain design based on multi-objective algorithm [J]. Journal of Electronic Measurement and Instrumentation, 2014, 28(4):373-380.
    [8] HU C, LI ZH, XU CH P, et al. Test scheduling with bandwidth division multiplexed for network-on-chip using refined quantum-inspired evolutionary algorithm [J]. Journal of Computational Methods in Sciences and Engineering, 2016, 16 (4): 927-941.
    [9] 朱爱军,陈端勇,许川佩,等. 光片上网络MRR故障检测方法研究[J].电子测量与仪器学报, 2017, 31(8): 1200-1205.ZHU AI J, CHEN D Y, XU CH P, et al. Research of MRR fault detection in photonic network on chip [J]. Journal of Electronic Measurement and Instrumentation, 2017, 31(8): 1200-1205.
    [10] GU H X, XU J, WANG Z. A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip[C]. IEEE Computer Society Annual Symposium on VLSI, 2009: 19- 24.
    [11] AHMED A B, YOSHINAGA T, BEN A. Scalable photonic network on chip architecture based on a novel wavelength-shifting mechanism[J]. IEEE Transactions on Emerging Topics in Computing, 2017, 5(4): 1-12.
    [12] XU Y, YANG J, MELHEM R. Tolerating process variations in nanophotonic on-chip networks[C]. Proceedings of the 39th Annual International Symposium on Computer Architecture, 2012: 142- 152.
    [13] LI ZH, MOHAMED M, CHEN X, et al. Reliability modeling and management of nanophotonic on-chip networks [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 20(1):98-111.
    [14] NITTA C, FARRENS M, AKELLA V. Resilient microring resonator based photonic networks[C]. IEEE/ACM International Symposium on Microarchitecture, 2011: 95-104.
    [15] VINEEL S, CHITTAMURU R, THAKKAR I, et al. HYDRA: Heterodyne crosstalk mitigation with double microring resonators and data encoding for photonicNoCs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(1): 168-181.
    [16] LI H, FOURMIGUE A, BEUX S L, et al. Towards maximum energy efficiency in nanophotonic interconnects with thermal-aware on-chip laser tuning [J]. IEEE Transactions on Emerging Topics in Computing, 2018, 6(3): 343-356.
    [17] ZHANG Z, YE Y. A learning-based thermal-sensitive power optimization approach for optical NoCs [J]. ACM Journal on Emerging Technologies in Computing Systems, 2018, 14(2):1- 21.
    [18] SARANGI S R, GRESKAMP B, TEODORESCU R, et al. Varius: A model of process variation and resulting timing errors for micro-architects[J]. IEEE Transactions on Semiconductor Manufacturing, 2008, 21(1):3- 13.
    [19] MIRJALILI S, GANDOMI A H, MIRJALILI S Z, et al. Salp swarm algorithm: A bio-inspired optimizer for engineering design problems [J]. Advances in Engineering Software, 2017(114):1- 29.