高频感应加热全数字锁相环的分析与FPGA实现
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摘要
全数字锁相环存在非线性部件,传递函数难以表达。通过Z域分析法选择合适的参数,分析了触发器型全数字锁相环的工作原理,得出Z域闭环传递函数,并以此研究了锁相环的全局稳定性和稳态误差,提出了各参数的约束条件。采用Xilinx ISim仿真与FPGA逻辑器件验证相结合的方法实现了一种单相全数字锁相环,并给出实验结果。结果表明,该锁相环具有锁相范围宽、动态响应快和稳态误差小的特点,具有一定的应用价值。
The transfer function of all digital phase-locked loop is difficult to obtain because of the non-linear parts. The operation principle of flip-flop all digital phase-locked loop was analyzed and the Z domain closed loop transfer function was obtained by the method of Z domain analysis with proper parameters. The global stability and the steady-state error of the phase-locked loop were studied and the parameter constraints relationship was built. A kind of all digital phase-locked loop was designed by using Xilinx ISim simulation and FPGA logical device,and the experiment results were given. The results show that this all digital phase-locked loop has a wide frequency range,fast dynamic response,small steady-state error and certain application value.
The transfer function of all digital phase-locked loop is difficult to obtain because of the non-linear parts. The operation principle of flip-flop all digital phase-locked loop was analyzed and the Z domain closed loop transfer function was obtained by the method of Z domain analysis with proper parameters. The global stability and the steady-state error of the phase-locked loop were studied and the parameter constraints relationship was built. A kind of all digital phase-locked loop was designed by using Xilinx ISim simulation and FPGA logical device,and the experiment results were given. The results show that this all digital phase-locked loop has a wide frequency range,fast dynamic response,small steady-state error and certain application value.
引文
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[8]刘亚静,范瑜.离散周期对伺服系统用全数字硬件化锁相环的影响机理[J].电工技术学报,2014,29(9):153-159.
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[2]郑继禹,张厥盛,万心平,等.锁相技术[M].西安:西安电子科技大学出版社,2012.
[3] Best Roland E.锁相环设计、仿真与应用[M].第5版.北京:清华大学出版社,2007.
[4]李亚斌,彭咏龙,李和明.自采样比例积分控制全数字锁相环的性能分析和实现[J].电工技术学报,2005,25(18):64-69.
[5]庞浩,俎云霄,王赞基.一种新型的全数字锁相环[J].中国电机工程学报,2003,23(2):37-41.
[6]肖帅,孙建波,耿华,等.基于FPGA实现的可变模全数字锁相环[J].电工技术学报,2012,27(4):153-158.
[7]古俊银,廖茂宇,陈国呈.一种高效的非线性电网数字锁相环[J].中国电机工程学报,2012,32(33):53-58.
[8]刘亚静,范瑜.离散周期对伺服系统用全数字硬件化锁相环的影响机理[J].电工技术学报,2014,29(9):153-159.
[9]刘亚静,范瑜.全数字硬件化锁相环参数分析与设计[J].电工技术学报,2015,30(2):172-179.
[10]刘亚静,范瑜.全数字硬件化正交锁相环建模与分析[J].电工技术学报,2015,30(15):148-155.
[11]胡春华,石玉.数字锁相环路原理与应用[M].上海:上海科学技术出版社,1990.
[12]胡寿松.自动控制原理[M].第4版.北京:科学出版社,2001.
[13]吴大正.信号与线性系统分析[M].北京:高等教育出版社,2005.