摘要
随着片上系统集成的IP核数目不断增加,传统总线和多层总线在实际应用中由于受到扩展性和带宽的限制,已无法满足片上系统IP核之间的通信需求。片上网络(Network-on-Chip, NoC)通信架构作为一种最有前景的替代技术,被提出并用来解决总线通信架构所面临的问题。NoC采用数据包传输的微网络来实现IP核之间通信。与宏观网络不同,NoC由于受到功耗、芯片面积、通信延迟等限制,对设计者提出了一系列新的挑战。
本文主要研究NoC设计中的关键技术问题,着重对片上网络IP核映射方法、路由算法以及片上路由器结构设计进行深入研究。本文的主要研究成果如下：
1.在NoC设计中,IP核映射是优化网络性能和能耗的有效方法之一。本文对蚁群算法进行了改进,实现了基于遗传蚁群的低能耗映射算法,该算法使用了与拓扑结构无关的启发信息,因此适用于多种拓扑结构的NoC映射问题。此外,为防止蚁群算法陷入早熟停滞状态,在改进算法中引入染色体杂交和轮盘赌选择等策略。实验结果表明本算法能有效解决多拓扑结构下的NoC映射问题,与基本蚁群映射算法相比,使用本算法对规模为3×3,4×4和5×5的NoC进行映射求解时,通信能耗可分别节约2.2%,6.3%和8.1%。
2.针对三维网格NoC拓扑结构特点,改进了片上通信能耗计算模型,并基于拓扑结构划分构造了一种快速低能耗映射方法SYMMAP。实验结果表明,与现有启发式映射算法相比,对于三维网格NoC映射求解,SYMMAP在映射速度、通信能耗等方面均具有较大优势。
3.不同映射结果会对NoC的最大通信延迟、功耗、可靠性、峰值温度等参数产生不同影响。NoC映射优化目标有时候需要多方面考虑,针对这个问题,本文综合考虑NoC映射中的热和功耗问题,使用多目标蚁群算法(MOACA)对这两个指标同时优化。MOACA算法能有效找到pareto优化前沿,实现映射后功耗和热平衡的同时优化。实验结果表明,使用MOACA获得的映射方案在降低芯片功耗的同时,也能降低芯片峰值温度。以多视窗显示应用(MWD)为例,与使用单目标功耗优化映射算法PBB所获得的映射方案相比,使用MOACA所获得的映射方案可在芯片功耗大致不变的情况下,峰值温度降低4℃左右。
4.路由算法对网络性能和通信效率有着重大影响,设计并实现路由算法是NoC设计过程中的关键步骤之一。针对三维网格NoC映射方案和被映射IP核的通信特征,本文基于通道依赖图设计了一种面向应用的路由路径分配方法。这种路径分配方法可在带宽约束下,实现路由路径自适应性最大化。此外,这种方法无需引入虚拟通道就可保证路由路径无死锁。通过分析和模拟证明,与常见无死锁路由算法相比,本方法产生的路由路径可有效提高网络性能。
5.NoC容错技术的主要目标是保证片上路由器产生故障时,片上通信仍不中断。容错路由是一种让NoC具备容错能力的技术手段之一。针对二维网格NoC中的多故障路由器问题,本文提出一种具有多故障容错能力的路由算法MFRT。 MFRT采用动态配置路由路径来容忍多故障路由器在NoC中的不同分布。理论分析和实验结果表明,MFRT能够加强系统通信可靠性,提供可观的NoC容错能力。与XY路由算法以及单故障容错路由算法相比,在路由器故障发生概率为10%的情况下,使用MFRT,片上通信可靠性分别能提高48.3%和9.56%。
6.针对片上缓冲消耗硬件资源多且使用效率低的问题,本文设计了名为PSBR的新型片上路由器。该路由器通过缓冲共享的方式提高缓冲的使用效率。为简化PSBR控制电路,本文通过分析片上通信负载分布,将部分端口共享缓冲策略应用于PSBR设计,并基于Verilog硬件描述语言实现了PSBR。综合结果和模拟结果表明,与典型片上路由器相比,在相同通信性能指标下,PSBR可分别节约15%的芯片面积和28.2%的路由器功耗。本文的研究成果为NoC设计与优化提供了一系列可行的方案,为进一步提高NoC的可靠性,可扩展性及实际运行性能提供了理论基础和实践经验。
With the number of integrated IP cores increasing in current System-on-Chip (SoC), limited by scalability and bandwidth in practical application, traditional bus or multi-layer bus cannot meet the needs of communications between IP cores. As the most promising alternative technique, Network-on-Chip (NoC) communication architecture has emerged to address the problems which the traditional on-chip bus has been faced with. NoC uses micro-network for inter-IP communications by packet. However, different from the macro-network, NoC puts forward a series of new challenges, including constraints in power, area and communication latency.
This dissertation makes an attempt to touch on the key technical problems related to NoC design. More precisely, the author makes an in-depth study on IP core mapping methodologies, routing algorithms and router architecture. The specific contributions are as follows.
1. For NoC design, IP core mapping is one of the effective ways to optimize network performance and energy consumption. In this dissertation, the author improves the ant colony algorithm and makes it possible to solve the low energy consumption mapping problem, which is based on genetic and ant colony (GAAC) mapping algorithm. This algorithm has used heuristic information, which is irrelevant to topological structure, so that it applies to NoC mapping problems of different topological structures. In addition, to prevent this algorithm from getting into premature stagnation, strategies such as crossover of chromosomes and roulette wheel selection have been introduced in GAAC mapping algorithm. The experimental results show that GAAC mapping algorithms could solve NoC mapping problems of different topological structures effectively. Compared with basic ant colony mapping algorithm, when this algorithm is used to solve mapping problem of the3×3,4×4and5×5NoCs, the communication energy can be saved respectively about2.2%,6.3%and8.1%.
2. Based on the topology characteristics of3D mesh NoC, the corresponding energy model has been improved. At the same time, a fast and low energy consumption mapping algorithm SYMMAP is proposed based on topology partition. According to the experimental results, when solving3D mesh NoC problems, SYMMAP takes great advantages over the existing heuristic mapping algorithm in terms of mapping speed and energy consumption.
3. Different mapping results may have different impacts on NoC metrics such as maximum latency, power, fault robustness, peak temperature etc. Different aspects need to be taken into consideration when optimizing NoC mapping objects. For this problem, this dissertation takes account of both power and temperature problems in NoC mapping, using multi-objective ant colony algorithm (MOACA) to optimize these two NoC metrics. MOACA algorithm can find the pareto-optimal front effectively and keep power and temperature in balance while being optimized. The results show that the mapping scheme by using MOACA can reduce the chip peak temperature as well as the chip power. Different from the mapping scheme while using PBB which is a single-objective power optimization mapping algorithm, the mapping scheme for Multi-Window Display (MWD) based on MOACA can make the peak temperature of chip reduce4℃, while the chip power remains stable.
4. Routing algorithm has a great effect on network performance and communications efficiency, so design and implementation of routing algorithm is one of the most critical issues during the NoC design. For the communications characteristics of the3D mesh NoC mapping scheme and the mapped IP core, this dissertation proposes an application-specific routing path allocation method based on channel dependency graph. This method can maximize the adaptivity of routing path under bandwidth constraints. What's more, the proposed method can guarantee deadlock freedom with no need of any virtual channel. According to the analysis and simulation, the proposed method provides better network performance when compared with other common deadlock-free algorithms.
5. The main objective of NoC fault-tolerant technique is to guarantee sustained communications when fault happens. Fault-tolerant routing algorithm is an efficient way to achieve fault tolerance in NoC. In this paper, to solve the problem of different faulty routers in2D mesh NoC, the author proposes a new routing algorithm MFRT with the ability of tolerating different faults. MFRT can tolerate different faulty routers distributions in NoC by reconfiguring routing paths dynamically. From the results of analysis and experiment results, it is clearly shown that MFRT can enhance the reliability of communications and offer considerable fault-tolerant capability. Compared with XY routing algorithm and single fault-tolerant routing algorithm, if the probability of faulty router is10%, MFRT can improve the reliability of on-chip communications by48.3%and9.56%.
6. For hardware resource overhead of on-chip buffer is large and the problem of low efficiency, a new on-chip router named PSBR is proposed. The proposed router maximizes the buffer utilization by allowing sharing them. To simplify the control circuits, a partially shared buffer strategy is applied to PSBR design by an analysis of on-chip communications load distribution, and PSBR is achieved based on Verilog HDL. The synthesis and simulation results show that PSBR can save15%of chip area and28.2%of router energy consumption, when compared to the typical on-chip routers under the same communications performance metrics.
The research results in this dissertation provide a series of feasible solutions for NoC design and optimization, and they offer theoretical basis and practical experience for further improvements in reliability, scalability and practical performance of NoC.
引文
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