摘要
在混合信号集成电路系统中,模数转换器(ADC)是一个关键的模块。由于流水线结构的ADC具有高吞吐率、高分辨率、低功耗、占用面积小等优点,因此研究流水线结构ADC具有非常重要的意义。
本篇论文首先简要介绍了流水线结构模数转换器的原理和结构,分析了各种非理想误差源和误差校准技术,并探讨了低功耗设计技术。最后采用流水线结构完成了一个1.8伏10比特100兆赫兹采样频率模数转换器的设计。
该模数转换器采用每级1.5位的9级流水线结构实现。电路最前端采用改进了的采样保持电路可以有效抑制输入信号共模电压的漂移,结合栅压自举采样开关的使用,电路的精度和线性度得到了较大的提高。单级增益自举的折叠型运算放大器保证了在获得高速、高增益的同时尽量降低其功耗。电路主要采用了以下三种方法来降低功耗:1.运放共享技术的使用可以减少近一半的运算放大器的数目,也就减少了大量的耗能元件。2.电路采用了分段的逐级电容缩减技术。3.各级的子模数转换器采用了没有直流功耗的动态比较器。
芯片采用TSMC 0.18μm,混合信号1P6M CMOS工艺,电源电压为1.8V。整体性能仿真表明:在室温下,采样频率为100MHz时,信号噪声失真比为59.12dB@1MHz input,58.4dB@10MHz input;无杂散动态范围为79.6dB@1MHz input,74.2dB@10MHz input;在整个奈奎斯特频率输入范围内,有效位数均超过9位。其核心电路功耗仅为62.5mW。
In mixed signal systems, Analog-to-Digital Converter (ADC) is a crucial portion. Pipeline ADC has the advantages of high speed, high resolution, low power consumption and small area, so it is very important to study the structure of pipeline of ADC.
Based on the analysis of some common architectures,this thesis presents a 1.8V 10-bit 100MHz pipelined Analog-to-Digital Converter.
It’s composed of a sample-and-hold circuit, eight stages with 1.5 bit per stage, and a 2 bit Flash ADC as last stage. There is a modified sample and hold circuit at the input of the ADC and the DC wandering of input is suppressed. With the bootstrapped sampling switch, the resolution and linearity of the system is improved . High speed, high gain are achieved by a single stage folded cascade opamp with gain-boosted technique consuming very low power. Besides, the following technque are taken to reduce power consumption: 1. The operational amplifier sharing technique is used to reduce the number of opamp, so the power consuming components is reduced. 2. The size scalling down technique is use to reduce power. 3. Power consumption is further reduced by using of dynamic comparator.
The ADC’s design is based on TSMC 0.18μm, mixed signal 1P6M process, which provides MIM capacitor. The simulation result shows: At the room temperature, 100MHz sampling frequency, it achieves SNDR(SINAD) of 59.12dB@1MHz input , 58.4dB@10MHz input, SFDR of 79.6dB@1MHz,74.2dB@10MHz; In the whole nyquist input frequency, the ENOB is over 9 bit. And the power consumption is 62.5mW.
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