摘要
随着集成电路系统级芯片的发展，要求模数转换器与微控制器共同嵌入到单一芯片中，形成具有独立功能的信号采集与处理芯片。针对这一需求，本文完成了一种模数转换器硬IP核的晶体管级电路设计以及物理版图布局设计。
该IP核由逐次逼近型模数转换器以及控制接口电路所构成。为了满足嵌入式应用的要求，对它内部的单元电路进行了若干创新设计。这些设计经理论分析和计算机仿真，证明是行之有效的。
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。三级差分放大器之间采用了开关电容电路耦合的方式，有效地消除了失调电压对比较器精度的影响。采用电荷泵电路提供开关管栅过驱动电压，带隙基准电路作为电荷泵稳定电压的输入，有利于改善开关电路的性能。
D／A转换器采用了两组行输出的电阻串结构，能有效地降低寄生电容对转换电压输出的影响。版图布局时采用了奇偶行识别电路的形式，用占有极小芯片面积的代价换取了布局的优化和简洁。
为了充分利用了嵌入式芯片丰富的系统资源，设计了简单实用的自测试电路，其测试向量和结果向量都可以通过总线被系统直接读取，系统执行相应的指令就可以完成相应的自测试过程。
对该IP核的全局仿真结果表明，所设计的模数转换器可以达到10位的精度，可以通过系统总线信号对8路信号输入通道以及5种采样速率进行选择控制，可以通过系统指令完成模数转换器的自测试功能。这些结果验证了该IP核可以适用于控制类芯片的嵌入应用设计。
A novel hard IP core of analog-to-digital converter is achieved, with the transistor level circuit and physical layout designed in detail.
The IP core contains a Successive Approximation ADC and interface control circuit. To meet the demand of embedded application, some innovative cell circuits are introduced, which have been approved by the theoretic deduction and computer simulation.
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
To cancel the offset-voltage of the comparator, a switch capacitance circuit is used between the three pre-amplifier stages. The charge pump circuit is used to boost the clock voltage of the switch transistor.
The DAC's output voltage can be exported by two groups of line-output structure. The simulation result shows this structure also can low the effect of the parasitic capacitances. A circuit is designed to define the odd and even line to meet the layout's simplification requirement.
To make full use of the system resource, an auto-test circuit is designed with test vector can be given through the internal bus and result vector can be detect by system. The auto-test process could be done by several instructions' executed.
Results of the IP core's simulation shows the ADC can achieve a 10-bit resolution. System has 8 input channel and 5 sample period selection with the control of internal bus. So the Analog-to-Digital Converter Hard IP core can be embedded in every type of micro-controller.
引文
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