摘要
随着自适应光学系统子孔径和校正单元数的不断增多、系统采样频率的逐步提高，对波前处理机的性能，尤其是系统中数据吞吐能力与延迟提出了更加严格的要求。但由于现有波前处理平台的数据传输结构为基于紧耦合并行总线互连结构，传输延迟较高，且无法实现传感器和监控数据的远距离传输，同时不利于今后大规模的扩展。因此，研究新的波前处理机互连结构，高速数据传输的工程实现，以及引入高速互连所带来的电气性能影响对波前处理机的发展具有重要意义，也是本文的核心内容。
在广泛总结与提炼前人工作成果的基础上，讨论了波前处理机中数据传输的各个重点环节。阐明了波前处理机中各数据处理单元的数据特征，将其间传递的数据划分为实时数据与非实时数据，并以此为线索，分析了现有平台中数据传输结构在未来应用的局限性。为解决现有平台中数据传输结构的缺陷，提出了一种以FPGA为核心的点对点松耦合数据传输架构，与原有传输架构相比，该结构具有硬件接口资源占用少、无总线竞争、传输延迟低、噪声抑制能力强的特点。
对波前处理机中实时图像数据对远距离、高速、低延迟传输要求的实现难题上，提出了一种基于数据流格式的实时图像数据传输方法，并设计了与其相应的基于光纤接口的自定义实时图像数据传输协议，该方法具有传输距离远、延迟低、硬件资源消耗低的特点。制作了实物板卡进行验证，结果表明其传输与协议处理延迟仅为413.5纳秒，有效传输带宽达到2.5Gbps，误码率低于10-12，该方法已在实际工程中得到应用。
在斜率与复原运算单元的互连结构上，讨论了基于并行总线和分布式互连结构对斜率运算与复原运算单元间数据交互的影响，结合波前处理任务流程，分别实现了针对单板卡与多板卡分布式互连结构中数据传输接口的设计，制作了实物板进行了验证，其中多板卡数据传输延迟仅为198纳秒，单板卡有效传输带宽达到2Gbps，误码率低于10-12，单板卡波前数据传输方法已在实际工程中得到应用。
在监控计算机与波前处理机远距离监控技术的研究上，对原有的基于CPCI紧耦合互连方式架构进行了改进，结合千兆位数据传输技术与嵌入式系统技术，实现了基于UDP与TCP/IP协议的千兆以太网远距离监控数据传输，并建立了实物板卡进行验证，结果表明在TCP/IP协议下传输速度达到220Mbps，UDP协议下达到600Mbps，满足监控数据的远距离传输要求。与原有基于标准PCI接口的监控数据传输方案相比，该方案能实现远距离数据交互，且无需额外的协议解析芯片，降低了硬件资源消耗，节省了成本，利于工程实现。
系统的研究了波前处理机中由于高频、高速器件引入而引起的信号完整性问题，采用场路混合建模的方法进行了系统级高速链路进行建模、仿真及优化。引入了基于DOE方法，分析并优化了实际处理机中高速串行链路，该方法在实际的处理机板卡研制中得到应用，经过实测，在该方法下设计出的高速链路在6.5Gbps速度下达到10-12误码率，满足波前处理机对高速串行链路的需求。
对波前处理机中电源同步开关噪声的来源进行了深入的分析，讨论了多种同步开关噪声抑制方法在波前处理机应用中的优缺点。在此基础上研究了电磁带隙结构在波前处理机电源噪声抑制中的应用，提出了一种基于螺旋谐振环结构的新型电源平面，制作了实物板卡与UC-EBG、Planar-EBG和传统电源平面进行了性能对比，结果表明新型电源平面获得了更高的同步开关噪声抑制带宽，在-40dB抑制深度下其阻带范围覆盖110MHz-5.8GHz，对比前两种电源平面噪声抑制性能分别提升95%与160%。此外，由于本结构保持了地平面的连续性，可以在保证抑制宽频电源噪声的情况下获得良好的信号质量，信号眼图的眼宽、眼高、抖动分别为281.6ps，494mV和44.5ps，与完整参考平面相比，信号质量几乎无畸变。
本文提出的波前处理机中高速数据传输和信号与电源完整性分析、设计方法大多已在工程中得到应用，为今后大规模自适应光学波前处理机中多单元互连及高速数据传输的设计与工程实现提供了有益的参考和帮助。
With the subaperture, correction units and sampling frequency of adaptiveoptics(AO) system increase, a more stringent requirement brought in datatransmission throughput and latency of wavefront processor. However, due to theexisting structure of the wavefront processing platform is a tightly coupled parallelbus-based interconnection structure which cannot achieve long distance sensor andmonitoring data transmission, and also go against large-scale expansion of AOsystem in the future. Therefore, the study of new interconnect structure, engineeringrealization of high-speed data transmission, as well as the electrical performanceimpact caused by the high-speed interconnect in wavefront processor is of greatsignificance to the development of wavefront processor in future and is also the corecontent of this thesis.
Arious key aspects of the wavefront processor in data transmission werediscussed based on summarizing the previous work. Illustrates the characteristics ofthe data in each wavefront data processing unit, the data transfer there between isdivided into real-time data and non real-time data, and as a clue to analyze thelimitations of existing data transmission structure in future applications. In order tosolve the deficiencies in the existing data transfer structures, a FPGA based point topoint loosely data transfer structure is proposed. Compared with the originaltransmission structure, the new structure has a feature of smaller hardware interface,no bus contention, low propagation delay and strong noise suppression.
For long-distance, high-speed and low-latency real-time image datatransmission of the wavefront processor, an image data stream based method isproposed. The corresponding fiber based custom real-time image data transferprotocol is designed, which has a characteristic of long transmission distance,low-latency and low resource consumption. The results show that the transmissionand protocol processing delay is only413.5ns, the effective transmission bandwidthis2.5Gbps, the error rate is less than10-12, and the method has been applied in theactual project.
The impact of distributed and parallel bus based interconnects structure for dataexchange between the slope and reconstruction unit is discussed. Single and multi board data transfer interface are achieved, the results show that multi board datatransfer delay is only198ns, single board effective transmission bandwidth is2Gbps,the error rate is less than10-12, and signal board data transfer method has beenapplied in the actual project.
Remote monitoring technology of wavefront processor has been researched, theoriginal CPCI tightly coupled based interconnect architecture has been improved.Combining gigabit data transmission and embedded systems technology, UDP andTCP/IP protocol based gigabit Ethernet remote monitoring data transfer realized. Theresults show that under the TCP/IP and UDP protocol the transmission speeds is220Mbps,600Mbps, respectively, the requirement of long distance monitoring datatransmission is met. Compared with the original scheme, the new one can achievelong-distance data exchange, and without additional protocol parsing chip, reducinghardware resource consumption, which will help the project implementation.
Hybrid Field-Circuit approach which incorporated3D full-wave EM andsystem simulation is adopted to analyze the signal integrity problems in wavefrontprocessor. DOE method is introduced to analyze and optimize the high-speed seriallinks in wavefront processor, the method has been applied in the development of theactual processor board, under this method, the measure results show that thetransmission speeds up to6.25Gbps, the error rate is less than10-12, the systemrequirements is met.
The sources of simultaneous switching noise in wavefront processor have beendiscussed in detail, a novel uniplanar electromagnetic band-gap structure is proposedfor suppression of simultaneous switching noise (SSN) in high-speed circuits on thisbasis. The new power plane mounted the features of spiral resonator, which cansuppress the SSN at lower and higher frequencies, respectively. Then full-wave andsystem simulation were applied to analyze the signal integrity (SI) performance. Thesimulated results display a good consistency with measured results and show theSSN suppression bandwidth is broadened from110MHz to5.97GHz under a noisesuppression margin of40dB, the SSN suppression characteristics are greatlyimproved in lower frequencies, approximately95%and160%of stopbandbandwidth improvement over the conventional UC-EBG and planar EBG powerplane is achieved, respectively, the SI of traces keep a good quality, eye open, eyeheight and jitter of SR-EBG board is281.6ps,494mV and44.5ps, respectively,which almost no distortion compared to the reference board.
Most of the proposed design methods of high-speed data transmission andsignal and power integrity analysis in wavefront processor have been practicalapplied in projects; it provides a useful reference and help for the large-scaleadaptive optics wavefront processor in high-speed data transmission interconnectiondesign and engineering implementation.
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