X、Ku波段宽带低噪声雷达跳频源的研制
详细信息    本馆镜像全文|  推荐本文 |  |   获取CNKI官网全文
摘要
频率合成器是电子系统的心脏,是决定电子系统性能的关键设备,在我们的生活中扮演着重要的角色。随着现代军事、国防及无线通信事业的发展,移动通信、雷达、制导武器、电子测量仪器和电子对抗等电子系统对频率合成器提出了越来越高的要求。世界各国都非常重视频率合成器的研究与应用,低相位噪声、高纯频谱、高速捷变和高输出频段的频率合成器已经成为频率合成发展的主要趋势。
     本课题来源于成都赛英科技公司与国营第七八六厂合作项目:X、Ku波段宽带低噪声雷达跳频源。课题要求输出频段较高,相位噪声较低(-95dBc/Hz@1KHz),且在宽带内实现跳频。根据频率合成理论,单环等简单的频率合成无法满足课题的要求。最终,课题采用了PLL+混频等综合频率合成技术。采用两个锁相环,一是数字环,实现主要的跳频功能;二是产生超低相位噪声的本振信号环,与数字环信号进行上混频实现所需频段,这样降低了数字环的倍频次数,减小相位噪声恶化,达到低噪声的效果。另外,数字环和模拟环同时跳频,覆盖整个宽带。
     本文首先介绍了频率合成的发展历史及其最重要的指标:相位噪声,然后介绍了锁相环频率合成技术的基本理论以及在具体系统设计中应该注意的问题。接下来详细叙述了本课题所采用的方案,各模块功能的实现,环路滤波器的设计方法及实际设计中遇到的困难,最后给出了系统的最终测试结果及改进措施。
Frequency Synthesizer is the heart of all the electronic systems. It determines the performance of the electronic equipments, plays the most important role in our lives. Along with the development of wireless communication, modern military and national defence, many systems such as radars, homing weapons, measure equipments need higher and higher performance of frequency synthesizer, wide frequency range, low phase noise, high spurious restraining, low jumping time and high working frequency. Most countries in the world have been playing more attention on the design of it.
     The subject comes from the cooperation project "X、Ku wide-band low noise radar hopping frequency synthesizer", between Chendu Sine Science and Technology Ltd. and No.786 national military factory. There are many difficulties in this project, such as high working frequencies, very low phase noise (-95dBc/Hz@1KHz ), wide band and hopping. Accordingly to the basic theory of frequency synthesis, we can't get the performance with just a singal PLL. Finally, the hybrid frequency sythesis technology: PLL+Mixer is adopted. We use two PLLs. One is a digital PLL which can achieve the mainly function of hopping. The other is to get a local oscillator with much lower phase noise.. Then we upconvent these two sigals in order to get high working frequencies we demanded. And both of these two PLLs have low multiples (N). So we get the low phase noise. Additionally, both of these two PLLs should hop synchronous to cover the wide band.
     At first, the history and the important specifications (phase noise) of the frequency synthesis technology is reviewed. Subsequently, the theory of PLL frequency synthesis technology are introduced. Then the scheme of this subject, the realization of each functional module, and some questions which must be paid attention to in the system design are presented. Finally, the testing results is given and analyzed in detail.
引文
[1] 白居宪.低噪声频率合成.西安:西安交通大学出版社,1994.
    [2] 迟忠君,徐云,常飞.频率合成技术发展概况.现代科学仪器,2006,3,21~24.
    [3] J. Tierney, C.M. Rader and B. Gold. A Digital Frequency Synthesizer. IEEE Trans. Audio Electroacoust, 1971, Vol. AU-19, p48.
    [4] 岳金山.分数分频锁相环频率合成器的研究:[硕士学位论文],成都:电子科技大学,2005.2~3.
    [5] 王玉珍,李袁柳.现代频率合成技术发展状况及分析.宇航计测技术,2003,Vol.23,No.3,61~64
    [6] 赵宏飞.4~8GHz宽带DDS锁相扫频源的研制:[硕士学位论文],成都:电子科技大学,2002.13~16.
    [7] 彭清泉.直接数字频率合成器(DDS)高穏高纯频谱频率源的研究:[硕士学位论文],成都:电子科技大学,1998,4~6.
    [8] 维迪姆.迈纳赛维奇.频率合成器理论与设计(郑绳楦等译).北京:机械工业出版社,1982,57~59.
    [9] 张玉兴.射频模拟电路.成都:电子科技大学出版社,2002,279~282.
    [10] Matthew M.Radmanesh.Radio Frequency and Microwave Electronics Illustrated.北京:电子工业出版社,2002,462~484.
    [11] 周骞.C波段低相位噪声调谐跳频源的研制:[硕士学位论文],成都:电子科技大学,2006.21~27.
    [12] Teresa M. Almeida, Moises S. Piedade. High performance analog and digital PLL design. IEEE, 1999, Ⅳ-394~Ⅳ-397.
    [13] 张厥盛,郑继禹,万心平.锁相技术.西安:西安电子科技大学出版社,1994,60~70、85~92.
    [14] 房玉东,吴顺伟.常用环路滤波器性能分析.泰安师专学报,1998,Vol.11 N0.6,47~50.
    [15] Guan-Chyun Hsieh, James C. Hung. Phase-Locked Loop Techniques-A Survey. IEEE. Transactions on industrial electronics, 1996, VOL. 43, 609-615.
    [16] Dean Banerjee. PLL Performance, Simulation, and Design. USA National Semiconductor, 2003, 41~42, 155~160.
    [17] 李尧,董姝敏,乔双.锁相环的改进与仿真.东北师大学报(自然科学版),2005,Vol.37,No.3,53~56.
    [18] 武永军,沈保锁.跳频频率合成器频率转换速度和频谱纯度的研究.天津工业大学学报,Vol.21,No.1,20~23。
    [19] Young-Shig Choi, Hyuk-Hwan Choi, Tae-Ha Kwon. An Adaptive Bandwidth Phase Locked Loop with Locking Status Indicator. IEEE. Radiotechnics Electronics Communications, 2005, 826~829.
    [20] Y. Fouzar, M. Sawan, Y. Savaria. Very short locking time PLL based on controlled gain technique. IEEE, 2000, 252~255.
    [21] 眭法川.锁相与频率合成。北京:国防工业出版社,1988,188~195.
    [22] J.克拉波,J.T.弗兰克勒.锁相和频率反馈系统(李兆寅译).北京:人民邮电出版社1982.87~98.
    [23] Kyoohyun Lim, Beomsup Kim. Optimal Loop Bandwidth Design for low noise pll applications, IEEE, 1997, 425~428.
    [24] 黄旭.C波段低相位噪声本振源的研制:[硕士学位论文].成都:电子科技大学,2005,36~42.
    [25] Analog Devices Inc. Fractional-N Frequency Synthesizer ADF4153. Data Sheet, 2004.
    [26] 刘光祜.锁相跳频源的极值相位裕量设计方法.电子科技大学学报,2001,Vol.30,No.6,551~554.
    [27] 习靖.锁相环路的稳定性研究.无线电通信技术,2002,Vol.28,No.1,55~56.
    [28] 狄青叶.锁相环频率响应特性及其稳定性分析的CAD方法.无线通信技术,2000,No.3,55~57.
    [29] Keese. William O. An Analysis and performance Evaluation of a passive Filter Design Technique for Charge Pump Phase-locked loops. AN-1001, National Semiconductor Wireless databook, 1996.
    [30] 张太江.现代微波PLL跳频源设计方法研究:[硕士学位论文].成都:电子科技大学,2002,32~37.
    [31] Hittite Microwave Corporation. HBT Digtal Phase-Frequency Detector, 10 - 1300 MHz w/5-Bit Counter, 10-2800MHz HMC440QS16G. Data Sheet, 2004..