摘要
微波频率源在通信、雷达、电子对抗、仪器和测量系统以及生物医学工程中有广泛的应用，它性能的好坏直接影响着系统的整体性能。频率稳定度是微波频率源的关键技术指标，本课题利用锁相环路，把短期频率稳定度高的介质振荡器与长期频率稳定度高的晶振相结合，得到长期和短期频率稳定度都很高的输出信号。影响短期频率稳定度的主要因素是相位噪声，即振荡器的随机调频或调相噪声。改善短期频率稳定度同器件的选择与电路的工作状态相关。
介质谐振器因其体积小、Q值高、结构简单、成本低廉、易于集成的特点，为微波电路设计带来了一些优异特性。用它来稳定振荡源的频率，可以在几乎不增加体积的情况下，获得提高频率稳定度和降低噪声的双重好处，而这是金属空腔谐振器无法做到的。本文首先对锁相环的基本工作原理和环路组成进行了简单的分析，然后详细分析了运用EDA仿真软件进行介质振荡器、低噪声放大器、功分器的设计。根据仿真结果，结合实际电路布局要考虑的问题，逐步向目标靠近，得到了较为满意的结果。根据指标要求，采用100MHZ恒温晶振作为参考源，由ADF4106、VCO和LF共同构成一个锁相环路，在4．8GHz的频点，测得相位噪声为-85dBc/Hz@10KHz，输出功率为10dBm，外形尺寸为79×80×20mm。
本课题的主要贡献：(1)采用闪烁噪声较低的HBT器件，共发射极结构，单电压供电，对变容管调谐介质振荡器进行了理论分析，采用并联反馈的结构，利用ADS和CST进行仿真和优化设计；(2)选用噪声系数较低的FET器件，共源极结构，双电源供电，利用ADS仿真软件设计了单级放大器。(3)对仿真结果与实验测试结果进行了对比，分析了产生偏差的原因以及在实际设计电路时应该考虑的问题。本课题的锁相点频频率源具有结构简单、可靠性高、易于集成、小体积、灵活性好等优点。
Microwave frequency source is needed for many communication, radar, electronic countermeasure, instrument, biomedicine projects and measurement applications. At the same time, its performance influences the whole capacity of a system directly. Stability of a frequency source is the key issue. Phase-locked loop is used, in which a short-term stability DRO combines with a long-term stability crystal oscillator, an output signal with high short-term and long-term stability is received ultimately. The dominating factor which influences the short-term stability is phase noise, that is stochastic frequency-modulated noise or phase-modulated noise. Improving short-term stability is interrelated with choice of devices and working state.
Because of small bulk, high-Q, compactness, low cost and easily integration, dielectric resonator is becoming increasingly common over the entire microwave frequency range. As a strongpoint, dielectric resonator possesses two advantages, improving stability and reducing noise while maintaining its bulk fixedness, whenas metal cavity is not reachable. We adopt the means of phase-locked loop to design. At first, we theoretically analyze the working principles and the composes of phase-locked loop, then exhaustively discuss the design of dielectric resonator oscillator, low noise amplifier and power divider using EDA simulation software. On the base of the guide line, we adopt 100MHz crystal oscillator as the referenced source. The phase-locked loop is composed of ADF4106, VCO and LF. The phase noise and output power of measurement results are respectively-85 dBc/Hz@10kHz and 10 dBm. The dimension of the frequency souce is 79×80×20mm.
The main contributions and creative points of this dissertation are as follows: (1) The low flicker noise transistor HBT, a common emitter configuration and a single de power supply are used. We analyze the theory of the varactor-tunable dielectric resonator oscillator. Design and optimization of the parallel feedback configuration are done using CST and ADS. (2) The low noise coefficient transistor FET, a common source configuration and a double electrical sources supplying power are used. Design and optimization of the single stage amplifer is done using ADS. (3) The simulation results and experimentation outcomes are compared and the reasons of resulting in windage are analyzed. The phase-locked dielectric resonator oscillator has the merits of simple configuration, high dependability, easy integration, small cubage, multifunction and etc.
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