摘要
A/D转换器是现实世界中模拟信号与数字信号沟通的桥梁。Pipeline结构作为集高精度、高转换速率、低功耗为一体的一种ADC，在高清晰数字音视频与现代无线通信领域有着很宽的应用范围。
本论文的目标是设计一种基于SMIC0.18um工艺，应用在音频、视频设备、通讯中频采样等领域的转换速度为50MSPS的12位的流水线型A/D转换器。本文给出了一种流水线结构模数转换器的设计方案，对流水线结构原理进行了分析介绍，论文从整体电路结构到具体电路的设计实现方面都作了许多工作。设计中采用了十一级流水线模式的结构:前十级每级.5位flash子模数转换器，第十二级为2位flash子模数转换器的流水线结构，采用冗余矫正的方法进行数字矫正。子模块电路设计中主要完成了高精度的采样保持电路、高增益带宽积的运算跨导放大器电路、低失调电压低功耗高速度比较器电路、1.5位和2位结构子模数转换电路以及数字校正电路、时钟产生电路的设计。对电路中存在的非理想因素进行了分析，并提出了降低这些非理想因素的方法。经过分析选取了最优化的电容大小，减小了版图面积，达到了低功耗的要求。
采用了cadence公司的Spetre仿真工具对电路进行了仿真，结果达到11.35bit精度。
Analog to digital converters is the bridge of the analog signal in the real-life world to digital signal。Pipeline ADC is a with high- resolution、high speed and low power dissipation structure , which have a wide variety of applications,such as High Definition Audio and Video Signal Processing and Wireless Communication systems.
This purpose of thesis submitted a design of a 12-bit 50 MSPS pipeline ADC, based on a 0.18μm SMIC CMOS process, which can be used in the field of video and audio instruments and the sample of intermediate frequency transceiver of communication. We did much work in the system architecture design and the transistor level module circuit design. A eleven stage pipeline architecture was used in this design: the preliminary ten stages 1.5 bit per-stage sub ADC, and the last stage is an 2 bit flash ADC. These eleven stages formed the ADC core. We accomplished the sub module circuits design, such as high resolution sample and hold circuit,high gain wide bandwidth operational Tran conductance amplifier, 1.5 bit per stage sub ADC, digital correction circuit, clock stabilization circuit, the transistor level band gap. Non-ideal factors in pipeline ADC are analyzed and some methods to decrease these non-ideal factors are presented. Selected the best capacitor by analyses ,so as to get the least layout area and low power dissipation。
The simulation results with cadence Spetre show that the circuit can get 11.35bit resolution.
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