摘要
随着数字信号处理和数据转换技术的发展,无线通信系统日益进步。软件可编程宽带无线收发机的商业化应用已具备可能。进一步地,可以由此发展出频带及通信协议由软件所定义的系统架构。这一发展对于无线基站尤为有利,主要体现在以下几点:降低基站成本、体积、复杂度和功耗,更重要的是可以支持各种不同的调制方式和协议。
但这种高性能收发机对应用其中的模数转换器(ADC)的性能提出了严苛的要求。对于该系统所覆盖的分辨率和采样率范围,基于开关电容电路(SC)的流水线结构模数转换器是最佳选择。本文着重设计了一款适应于无线蜂窝基站应用的具备高速高精度以及高无杂散动态范围(SFDR)的流水线模数转换器。该模数转换器具备14比特分辨率和100兆采样/秒转换速率。文章首先简要介绍了ADC的应用环境及发展现状;之后从系统角度,讨论了高速高精度流水线模数转换器的基本架构,分析了各种电路非理想因素并提出了一种数字后台校准算法以减小转换中的非线性;接着从电路实现的角度,详细阐述了关键模块电路的分析和设计,如改进型的栅压自举(bootstrap)采样开关、增益自举(gainboosting)两级密勒补偿运算放大器、高速低回踢噪声比较器、低抖动时钟电路等;在本文最后,介绍了版图设计,测试方法及测试结果。
本文中所设计的ADC采用SMIC的0.18μm单层多晶六层金属的CMOS工艺实现,芯片核心面积为7.16mm~2,在1.8伏电源电压下核心功耗为220mW(不包括数字输出驱动缓冲器)。测试结果显示,数字后台校准,该ADC的微分非线性度和积分非线性度分别为+0.18/-0.18LSB和+1.1/-0.6LSB,达到14比特线性度。在100兆采样率下,该ADC对8.1兆赫兹的输入信号频率,可以达到75.1dB的无杂散动态范围(SFDR)和66.1dB的信号噪声失真比(SNDR);对502.8兆赫兹的输入信号频率,可以达到74.5dB的无杂散动态范围和61.5dB的信号噪声失真比。
Radio architecture design has changed with developments in digital signal processing and data conversion,allowing the commercialization of the wideband software programmable radio transceivers.Further,these developments allow the architectures whose frequency channels and protocols can be defined by software.This is especially relevant for wireless base-stations,where it offers significant benefits:reducing the cost,size,complexity,and power consumption of a base-station.More important,it can support a variety of modulation schemes and protocols.
These high performance transceivers place very stringent demands on the analog-to-digital converter(ADC).The pipelined ADC architecture,based on the switched capacitor(SC) technique,has most successfully covered the widely separated resolution and sample rate requirements of these receiver architectures.This thesis focuses on the design of a high speed,high resolution and high spurious free dynamic range(SFDR) pipelined ADC for cellular base station applications.This ADC is with 14-bit resolution and 100MS/s conversion rate.At the beginning of the thesis,the application,state of art and trend of ADC is introduced.Then from the view of system,the architectures for realizing high speed high resolution pipelined ADCs are discussed,the non-ideal factors are analyzed and a digital background calibration method is proposed to mitigate the non-linearity in conversion.From the view of circuit,detailed analysis and design flow of the key blocks are presented.These blocks consist of improved bootstrap sample switch,miller compensated gain-boosted two-stage amplifier,fast low kick-back comparator and low-jitter clock circuit etc.At the last of the thesis layout techniques,test setup and measured results are introduced.
The proposed ADC is fabricated in SMIC 0.18μm one poly six metal CMOS Mixed-Signal process occupying 7.16 mm~2 die area and consuming 220mW(excluding output driver) at 1.8V power supply.Measurements shows that,after calibration,the ADC achieves 14-bit linearity with +0.18/-0.18LSB DNL and +1.1/-0.6LSB INL.At 100 MS/s, the ADC acheives 75.1dB SFDR and 66.1dB SNDR for an input signal of 8.1 MHz,and maintains 74.5 dB SFDR and 61.2 dB SNDR for an input signal of 502.8 MHz.
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