摘要
随着数字通信系统的发展,高速数字处理系统对模拟信号和数字信号之间的转换要求越来越高。高速模数转换器已经成为当今模拟集成电路的研究热点
本文设计了一个12位40 M流水线结构模数转换器(ADC)。综合考虑到面积、速度和功耗,该ADC由4级分别为5位、3位、3位、4位流水线级构成。从影响ADC性能的各种非理想因素入手,在逐一改善这些非理想因素影响的过程中得到电路的具体结构。
本文主要针对采样保持电路和静态功耗较小的动态比较器进行研究,ADC中每个模块都通过了功能仿真,达到了所需要的性能指标。本设计可用于信号处理,或作为SOC芯片的一个IP核。
With the development of modem digital communication systems,high-speed digital processing system creates a great demand for high conversion rate between analog signal and digital signal,and high-speed ADC has gained a lot of importance and interst.
A 12-bit 40 MS/s pipeline A/D converter is designed in this paper.Extensively consideration for the speed,area and its power dissipation,the structure design is consist of 4 stages pipelined containing 5 bit,3 bit,3 bit,4 bit individually.Analyzing the nonideal factors at the beginning and with improving all of this one by one the architecture of ADC is got.
This thesis focuses on the research of S/H circuit and low-power dynamic comparator. All modules in the ADC are successfully simulated,and reach the demands of ADC.This chip can be used in signal process or embedded in SOC chip as an IP core.
引文
[1]Baker R J.CMOS Mixed-Signal Circuit Design.IEEE Press,Wiley interscience,2002,312-385.
[2]欧阳文伟.ADC和DAC工作原理比较和发展现状.湖北教育学院学报.2005,3,22(2).67-69
[3]Yoshii Y,Asano K,Nakamura M,et al.An 8b 100MS/s flash ADC.ISSCC Dig.of Tech.Papers,San Francisco,CA:IEEE Solid-State Circuits Socity,1984,58-59.
[4]Vorenkamp P,Roovers R.A 12-b,60-Msample/s cascaded folding and interpolatingADC.IEEE J.Solid-State Circuits,1997,32(12):1876-1886.
[5]Boser B E,Wooley B A.The design of Sigma-delta modulation analog-to-digital converters.IEEE J.Solid-State Circuits,1988,23(6):1298-1308.
[6]Signore B P,Kerth D A,Sooch N S,et al.A monolithic 20-b delta-sigma A/Dconversion.IEEE J.Solid-State Circuits,1990,25(6):1311-1316.
[7]Behzad Razavi,Wolley B A.A 12-b 5-MSample/s Two-Step CMOS A/D Converter.IEEE J.Solid-State Circuits,1992,27(12):1667-1678.
[8]Abo A M.Design for Reliability of Low-voltage,Switched-capacitor Circuits.U.C.Berkeley Doctoral Thesis,1997.
[9]Song B S,Tompsett M F,Kadaba R L.A 12-bit 1-Msample/s CapacitorError-Averaging Pipelined A/D Converter.IEEE J.Solid-State Circuits,1988,23(6):1934-1944.
[10]欧俊雯,闵昊,等。一个10位流水线操作CMOS A/D变换器的设计。复旦大学硕士学位论文,1998.
[11]Cho T B,Gray P R.A 10b,20 Msample/s,35mW Pipeline A/D Converter.IEEE J.Solid-State Circuits.1995,30(3):166-172.
[12]Park Y I,Karthikeyan S,Tsay F,et al.A low power lObit,80MS/s CMOS pipelinedADC at 1.8V.IEEE ISCAS,Sydney Australia:IEEE Circuits and Systems Society,2001,576-579.
[13]Cline D W.Noise,Speed,and Power Trade-offs in Pipelined Analog to DigitalConverters.U.C.Berkeley Doctoral Thesis,1994.
[14]李福乐。适宜于系统集成的高速高精度模数转换电路设计技术研究。清华大学工学博士论文,2003.
[15]Boris Murmann,B.E.Boser.A 12b 75MS/s Pipelined ADC using Open-LoopResidue Amplification.ISSCC Dig.Tech.Papers.2003.
[16]欧阳文伟.ADC和DAC工作原理比较和发展现状.湖北教育学院学报.2005,3,22(2).67-69。
[17]吴大正主编,杨林耀,张永瑞编.信号与线性系统分析.第三版.高等教育出版社.1998。
[18]Phillip E.Allen:Douglas R.Holberg著;冯军,李智群译;“CMOS模拟集成电路设计,第二版,电子工业出版社,2005年。
[19]毕查德.拉扎维.模拟CMOS集成电路设计.西安:西安交通大学出版社.2003.334-345。
[20]Mikko Wa(?)ari.Integration of High-speed CMOS Sample-and-Hold Circuits:[Master Theses].Helsinki:Department of Electrical and Communications Engineering Helsinki University of Technology,1999.15-29。
[21]Kamath B Y,Meyer R G,Gray P R.Relationship Between Frequency Response andSettling Time of Operational Amplifiers[J].IEEE J Solid-State Circuits,1974,9(12):347-352.
[22]Miao G Q.Tang P S.Design considerations for a high performance OTA with fullydifferential gain enhancement.Intl Conf.on SSTCT.Beijing,P.R.C.1995,115-118.
[23]David Villiam CIine.Noise,Speed,and Power Trade-offs in Pipelined Analog to DigitalConverters.[Doctor' s degree thesis]University of California at Berkerly:1999.
[24]Ho J Cam Luong H.A3-V,1.47nW,120-MHz compararor for use in a pipelined ADC.Circuits and System,1996,IEEE Asia Pacific Conference on,18-21 Nov 1996 Page(s):413-416.
[25]Robert C.Taft,Chris A.Menkus,Maria Rosaria Tursi.ADC with 7.26 ENOB at Nyquist Frequnency.IEEE Journal of Solid-state Circuits,2004 Vol.39,NO.12:2107-2115.
[26]K.J.McCall,M.J.Demler,and M.W.Plante.A 6-bit 125MHz CMOS A/D Converter.in Proc.CICC,May 1992,PP.168.1-16.8.4.
[27]Das M.Improved Design Criteria of Gain-Boosted CMOS OTA with High-SpeedOptimizations[J].IEEE Trans on Circuits and Systems Ⅱ,2002,49(3):294-297。
[28]Flandre D,et al.Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS StagesUsing Symbolic Analysis and gm/ID Methodology[J].IEEE J Solid State Circuits,1997,32(7):1006-1012
[29]Moon U K,Song Background digital calibration techniques for pipeline ADC' s IEEE Trans.Circuits Syst.Ⅱ,1997,44(2):102-109
[30]Mayes M K,Chin S W.A 200Mw,1Msample/s,16-b pipelined A/D converter with on-chip 32microcontroller.IEEE J.Solid-State Circuits,1996,31(12):1862-1872