摘要
集成电路已经进入系统级芯片(SOC)阶段。在通信、视频处理等混合信号系统中,高速、低功耗ADC是一个十分关键的部分。与其他结构相比较,流水线(PipelinedArchitecture)ADC结构的特点是既能实现高速又能实现相当高的分辨率。本设计采用0.18μm 1P6M CMOS混合信号生产工艺,实现转换精度为10比特、转换速率为40 MHz的A/D转换器。
本文首先对流水线型模数转换器电路作了系统的介绍,对ADC中的功耗抑制技术进行了理论分析,同时提出了从结构到电路的低功耗流水线型ADC设计方法和标准:1.采用SHA-Less设计,降低了ADC的级数。2.选择最优的单级分辨率及电容逐级递减,从而降低了功耗。3.对电路核心模块运放和比较器进行功耗优化设计。
最后通过Cadence设计软件完成了10比特流水线型ADC电路的设计,采用中芯国际(SMIC)0.18μm 1P6M CMOS模型进行版图后仿真。在最终的芯片测试结果中,输入信号为9 MHz,采样频率为40 MHz时,转换精度能够达到8.7 bit有效位数,满足系统要求。在1.8 V电源电压下的功耗为48 mW。
With the development of IC design and process,the integrated circuit have enter into the system-on-chip (SOC) stage. In the communications, video processing, and other mixed-signal system, the high-speed, low-power ADC is a very crucial part. Compared with other structures, pipeline ADC structure can achieve both high-speed and very high resolutions. In this paper,a 10 bit 40 M pipelined ADC was designed in SMIC 0.18 urn process.
The first chapter of this article made systematic introduction of ADC, then discussed the design methodology and criteria on low-power dissipation high-speed pipelined ADC through theoretical analysis of power restrain of ADC. We will present the design consideration from architecture to circuit. 1.we put the emphasis on SHA-less front end structure, 2. optimized resolution per stages and stage scaling.3. In circuit level, the power optimization was performed for the core modules of operational amplifier and quantizer.
Using SMIC (SMIC) 0.18μm 1P6M CMOS PDK as the post-simulation model, The test result reveals that the ADC designed with this method achieves the 8.7 bit at full speed of 40MHz when input frequency is 9 MHz.The power is 48 mw.
引文
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