摘要
二步流水线式ADC是目前ADC最主要的产品之一，主要应用在速度和精度兼顾的领域，如通讯中的无线局域网，消费产品中的手机、高清晰度电视等。
本文设计完成了一种基于数字校正的二步流水线式模数转换器，它以传统二步式ADC结构为基础，结合了Pipeline ADC的流水线工作方式和数字校正技术，相比于传统的二步式ADC，在两方面进行了改进。首先引入数字校正技术，在降低对前级电路设计要求的同时增强了系统的容差能力；其次，增加两个采样保持电路使系统工作在流水线方式下，提高了系统的数据吞吐能力和转换速率。
系统中重点设计的模块包括：采样保持电路、两级量化器和数字校正电路。采样保持电路采用全差动开环结构以满足系统所需的速度，同时加入单位增益放大器、减小β的射极负反馈电流源以及伪MOS开关以减小误差提高精度。两级量化器是Flash结构ADC，采用全差动电阻梯加比较器网络的结构，跟传统Flash结构相比，其特点是积分非线性小、对电阻匹配的要求低、能有效地抑制共模噪声。量化器中的比较器采用输入级放大加预放大锁存结构，实现了高速度和高的回馈噪声抑制。数字校正电路将正冗余算法和负冗余算法相结合，并在余量正向溢出的情况下对第一级量化器输出采用温度码-补码的编码方式，降低了后级电路的复杂度。
采用上华0.6μm BiCMOS工艺模型，工作电压5V，在Cadence的SPECTRE下对各单元电路进行了设计和仿真，达到了系统需要的性能指标，在采样频率为40MS／s时，该ADC可达到10位的分辨率。
Two-step pipelined analog to digital converters (ACDs), one of the most popular ADCs, are mainly used in the fields which resolution and speed are both required, such as wireless local area network (WLAN), mobile phone, high-definition television (HDTV), et al.
This dissertation introduces the design of a two-step pilelined analog to digital converter based on digital calibration. The ADC combines the pipeline and digital calibration technology of pipeline ADCs' with a basic structure of conventional two-step ADC.Compared with conventional two-step ADC, the performance of the ADC designed in this dissertation has been improved at two aspects. Firstly, digital calibration technology is used to improve the error-tolerance ability and reduce the complexity of circuit design. Secondly, in order to enhance data-throughput and conversion rate, pipeline technology is introduced by using two more track and hold circuits.Important circuits in this system are track and hold circuits, two quantizers and digital calibration circuit. Full-differential open-loop architecture is employed in track and hold circuits, to meet a high speed the system required. Meanwhile, unit-gain amplifier, dummy MOS switch and current mirror with beta helper and emitter degeneration are also used in track and hold circuits to reduce error and increase accuracy. Two quantizers are Flash ADCs, using differential resistor ladder and comparator-network structure. Compared with conventional Flash ADC, the differential resistor ladder quantizier can reduce the integral nonlinearity error and the resistor matching requirement. The comparator designed in the quantiziter can work at a high speed but has a low kick-back noise. Both negative and positive redundance arithmetic are combined in digital calibration circuit. When the redundance overflows positively, thermo-code to binary-code coding mode is used in the first quantizer ADC1 to reduce the complexity of digital calibration circuit.
All circuits in this system are designed in 0.6μm BiCMOS technology, with 5V supply voltage, and simulated in Cadence-Spectre. Simulation results indicate that all circuits designed above have good performance and satisfy the requirement of the system. Finaly, the ADC designed in this dissertation can achieve 10-bit resolution at 40MHz sample rate.
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