摘要
几乎所有的现代通信系统都需要稳定的周期信号—时钟来提供基本的时序基础。周期时钟信号的产生由于受制造工艺的限制成为高速通信系统急需解决的问题，这些时钟信号一般由频率综合技术产生。本文系统研究了锁相型频率综合器的基本工作原理、线性建模、环路噪声性能，从片内集成易行性、小面积、多相位角度出发，选择环形振荡器作为电路核心，研究和实现了两个低成本高性能频率综合器的完整设计。
首先，从锁相技术基本理论出发，详细推导了锁相环二阶线性模型的输入暂态响应，从理论上指导环路阻尼因数的选取，并对三阶开环(波特图)和三阶闭环(根轨迹)稳定性判定做了详细分析与验证，指出三阶开环模型中环路参数与直接闭环中参数的差异以及适用范围。同时又从环振适用性角度出发，有针对性地推导了几种振荡器噪声模型，选择经过Eken修正的DaiLiang模型作为环形振荡器行为级设计的噪声估计基础，并用电路级仿真结果进行验证。
然后，系统总结了现有环振的典型结构，并针对高频应用下环振VCO的工艺和温度相关频偏与小增益的矛盾，提出并设计一种新型基于多通路交叉耦合结构的可选负载延迟单元，在避免太大VCO增益的前提下，有效解决了高频环振在极端工艺角下增益曲线无法覆盖中心频率问题，并将其成功应用于高频环振型频率综合器的设计中。
接着，在实现以太网低抖动低功耗高性能的频率综合器设计中，为了有效解决超精细相位性能与成本的矛盾，提出一种新颖的动态电压模相位内插电路，与8级环振VCO相配合，为系统同时满足发送与接收需求起到至关重要的作用。芯片采用0.18um标准CMOS工艺，电源电压为1.8V。电路经流片验证，性能稳定优良(125MHz时钟rms jitter≈11ps@25MHz晶振输入rms jitter≈16ps)，且有较小的功耗和面积。
最后，针对高频环振型频率综合器设计这一挑战，我们从系统的行为级参数设定和模块噪声估算着手，同时考虑低噪声和低功耗的权衡，设计出一个综合指标优良的高频(～5GHz)环振型频率综合器。它采用了文中介绍的自动校准频偏的新型VCO，并配合差分电荷泵(及共模反馈)改善控制电压共模纹波。在实现差分控制电压转单端时，又设计一个新颖的DTOS(Differential-To-Single)模块，不仅提供几乎工艺无关的精准增益，调节控制电压的电平至VCO需要的电压范围，而且又产生一个额外的高阶环路极点，滤除环路中高频噪声。芯片采用0.18um标准CMOS工艺，核心模块电压为1.8V。在任意波形发生器作为参考时钟条件下，测试得到正确的锁相功能和较好的相位噪声(-100dBc／Hz@1MHZ，carrier=5.4GHZ)及积分相位误差(＜2.3ps)。
Almost all modern communication systems need stable periodic signals, clocks, to provide basic timing for functions. The generation of stable periodic signal has been an urgent issue to be resolved due to the fabrication process limitation. This thesis has systematically researched the PLL based frequency synthesizer from the aspects of primary theory, linearly modeling and loop-filter performance. Also two low-cost high-performance frequency synthesizers have been designed where ring oscillator is chosen as the core circuit considering the factors like feasibility of integration, small area and multiple phases.
First of all, detailed reasoning procedure of input transient response for PLL 2-order linear model has been obtained to guide the selecting of loop damping factor, as well as analyze and validate the stability of 3-order open-loop and close-loop, indicating the difference and application range between 3-order open-loop parameters and direct close-loop ones. Meanwhile, the thesis has summarized several noise models for oscillator from the side of applicability, choosing Eken-amended DaiLiang model as noise estimation basis for ring oscillator behavior-level design and verifying by transistor-level simulation.
Secondly, systematic summarization has been given on the available typical ring oscillator structure. The conflict between a small gain of Voltage Controlled Oscillator (VCO) and large frequency variation due to process and temperature fluctuation in high frequency application leads to the design of a new multi-pass cross-coupled delay cell with selectable loading controlled by automatic switches. This design has effectively resolved the issue that the gain curve of high frequency ring oscillator can not cover the centre frequency under extreme process corners.
Then, in order to trade off between the cost and performance of super-fine phase when realizing the low-jitter low-power high-performance frequency synthesizer for Ethernet application, a novel dynamic voltage-mode phase interpolator with 8-stage differential ring VCO has been provided satisfying the requirement of transmitter and receiver simultaneously. The chip has been implemented in SMIC 0.18-um standard CMOS process and achieved an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power dissipation is smaller than 4mW from a 1.8V supply voltage.
Finally, a high-frequency frequency synthesizer which adopts the new multiple-pass ring VCO with frequency calibration in different process corners has been desinged. The whole design flow includs behavior-level, circuit-level, layout, PCB and measurement. Besides the ring VCO, the loop uses differential Charge Pump (CP) and a novel Differential-To-Single (DTOS) module to convert differential output of CP to single one. The DTOS has a precise gain which adjusts equivalent VCO gain in loop. Meanwhile it can change the control voltage level to cater for VCO and produces an additional high-frequency pole for noise filtering. The chip was implemented in SMIC 0.18-um standard CMOS technology and core power supply is 1.8V. It achieves good phase noise and jitter performance (-100dBc/Hz@1MHz, carrier=5.4GHz) by using waveform generator as the reference clock.
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