摘要
随着VLSI工艺水平的提高,如今能够把整个电子系统集成到一块或几块芯片上(SoC)。SoC的出现能够在改善系统性能的同时减小系统的功耗、尺寸和成本。SoC设计成败的关键在于其中的RISC微处理器的设计。同时随着半导体工艺技术的提高、体系结构技术的不断发展以及应用需求的不断提高,对高性能嵌入式微处理器产品的需求量也越来越大。
本文在介绍了各种商业主流RISC微处理器的技术特点后讨论了一种32位高性能RISC微处理器的设计方法,重点在于其逻辑设计,包括:指令集结构设计、RISC CPU设计、层次化存储器系统设计和其它功能单元设计。随后我们对RISC微处理器进行了功能验证,它包括两个方面:系统级仿真与FPGA硬件验证。实验表明,我们所设计的电路达到了预期的目标,并且在速度、面积等指标上有着较好的性能。
本文提出了一种对集中式控制器单元进行划分的方法并根据该方法确定了RISC CPU的体系结构。这种结构不仅利于进行调试和扩展而且流水线的暂停信息不会在多个流水段内进行传递,因此对流水线的速度不会附加额外的负面影响。
本文提出了一种完全去掉由RAW冒险在流水线中所引起的“气泡”的方法。
本文提出了一种显著缩短程序的执行时间的方法。当转移指令处于指令译码段时就能够判断转移发生与否和确定下一条要取的指令的地址,这使得在转移指令之后只需插入一条空指令。这种方法显著地缩短了程序的执行时间。
本文提出了流水线暂停的两条原则并根据这两条原则产生了流水线中各个流水段的暂停信号。仿真波形表明,这些信号能够使流水线正确地暂停与恢复。
本文采用了不同的方式产生从指令MMU送往指令Cache和从数据MMU送往数据Cache的是否可缓存标志信号。在任何情况下指令存储器所对应的地址空间都是可缓存的。这在功能上是正确的,同时减少了指令存储器的访问次数和去掉了一个异步环路。这改善了整个系统的时序。
本文研究了RISC微处理器的低功耗设计技术并给出了一种支持动态和静态功耗管理的功耗管理单元的设计方法。
本文研究了RISC微处理器对WISHBONE SoC接口的支持并给出了一种采用
WISHBONE协议的总线接口单元的设计方法。
本文介绍了在进行系统级仿真时所采用的两种配置管理方法。通过这两种仿真管理方法,对于一种特定的仿真,仿真环境的使用者能够以最快的速度决定在该仿真中要使用哪些模型从而提高了仿真效率。
最后,给出了设计的FPGA硬件验证方案。比较了系统级软件仿真与FPGA硬件验证两种方式所能得到的吞吐率并论证了FPGA硬件验证的必要性。
总的来说,该微处理器在应用方面具有很好的性能,并且实现简单,规模可扩展性好,具有开放的SoC接口。
Technology advances are providing overwhelming capability to integrate the whole electronic system into a single chip or a chip-set. The SOC (system-on-a-chip) paradigm reduces system power, size and cost as well as improves system performance. The key to the success of SoC design is the RISC microprocessor inside. And with the boost of semiconductor technology and the development of architecture technology, new applications need more and more high performance embedded microprocessors.
This paper discusses the design methodology of a 32-bit high performance RISC microprocessor after various commercial mainstream RISC machines are introduced. It includes the following aspects: design of Instruction Set Architecture; design and implementation of RISC CPU﹑hierarchy memory system and other functional units with the emphasis is logic design. Functional verification that consists of system-level simulation and FPGA hardware prototyping is preceded and the results show goal is achieved and the performance characters such as speed and area of the design is good.
This paper presents a new approach to partition the central controller unit and the architecture of the RISC CPU is determined based on the proposed approach. Compared to the traditional architecture, this architecture is easier to be debugged and extended. Moreover, the pipeline stall information doesn’t traverse through multiple pipeline stages and it doesn’t impact on the pipeline speed.
This paper presents an approach to completely remove the bubbles in the pipeline caused by the RAW hazard.
This paper presents an approach to shorten the program’s execution time. Whether branch is taken can be judged and what is the next instruction to be fetched can be determined when the branch instruction is still in instruction decode stage. Thus, only a NULL operation is inserted after the branch instruction and the execution time of program can be significantly decreased.
This paper also presents two principles to stall the pipeline and freeze signals corresponding to various pipeline stages are generated accordingly. The simulation waveform shows that the pipeline can be correctly stalled or unstalled by these signals.
Different methods are adopted to generate the cache-inhibit flag according to whether
it is sent to the instruction cache from the instruction MMU or it is sent to the data cache from the data MMU. The address space corresponding to instruction memory is always indicated cacheable, which is correct in function. The number of instruction memory access times is decreased and an asynchronous loop is removed to improve the timing of the whole system.
Low power design technology in microprocessor is researched and a design methodology that supports dynamic and static power management is proposed.
WISHBONE SoC interface is researched and the design methodology of a bus interface unit that is completely compatible with the WISHONE bus protocol is provided.
This paper presents two approaches used in system-level simulation to manage configurations. Through these two approaches, the user of the simulation environment can determine which models are necessary in a special simulation with the least time and thus, the simulation efficiency is improved.
The scheme of FPGA hardware implementation has been given at the end of this paper. The throughputs of software simulation and hardware emulation are compared and the essence of FPGA hardware prototyping is verified.
In general, this RISC microprocessor based on design principle achieves high performance with low hardware cost. It has good scalability and open SoC interface and can be easily integrated into an electronic system.
引文
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