摘要
横向高压器件是高压集成电路的关键器件,受到了众多学者深入的研究。随着半导体技术的快速发展,功率器件和常规低压器件等比例减小。由于漂移区电场的二维本质,一维模型不能深入揭示其物理机理。对于采用终端技术的高压器件,由于边界条件的复杂使二维模型求解困难,因此反映横向和纵向电场耦合作用的电场和击穿电压模型亟待建立。高压器件中击穿电压和导通电阻之间的折衷关系,是众多器件设计者研究的热点。设计具有与CMOS工艺兼容的薄漂移区高压器件是功率半导体技术的一个重要发展方向。
本文研究了薄漂移区高压器件的二维耐压模型和改善击穿电压和导通电阻折衷关系的新结构。首次提出了薄漂移区D-RESURF器件二维表面电场模型和薄漂移区阶梯掺杂器件耐压模型。提出三种高压器件新结构:薄型双漂移区高压器件、P埋层低掺杂漏SOI高压器件和双面阶梯埋氧层PSOI高压器件,并进行部分实验研制。
基于Poisson方程,建立表面注入P_b区D-RESURF器件二维表面电场模型。随着漂移区的减薄,纵向电场对表面电场的调制作用显著增强。基于该模型,分析结构参数对表面电场和纵向电场耦合作用的影响,给出获得最大击穿电压和最小导通电阻的优化条件,计算了漂移区厚度和长度与击穿电压的关系。在理论的指导下,成功研制了900VD-RESURF器件。提出漂移区不完全耗尽型S-RESURF器件二维耐压模型,分析器件分别在P_(body)N_e结、N~+N_e结和体内PN结发生击穿的情况。在满足最优表面电场条件下,导出反映电荷共享效应的二维RESURF判据。
建立薄漂移区阶梯掺杂器件二维耐压模型。由于横向电场相互耦合,在不同掺杂区界面处产生新的电场峰。在纵向电场的耦合作用下,电场峰值降低,漂移区表面电场趋于均匀。借助此模型,研究了结构参数对漂移区电荷共享效应的影响,给出了器件参数之间的优化关系。表面阶梯掺杂器件正向导通电流大部分流经表面,导通电阻降低。阶梯掺杂漂移区器件改善了器件在导通电阻和击穿电压之间的折衷关系,且具有较好的工艺容差。
提出薄型双漂移区结构。由于表面注入N~-层掺杂浓度较高,漏电流绝大部分流经表面,使导通电阻下降。在沟道区下方采用P离子注入埋层,改善漂移区电场分布,P埋层电场的调制作用在表面电场中引入新的电场峰,使表面电场分布均匀。在漂移区掺杂剂量相同的情况下,随着表面N~-层厚度的降低和掺杂浓度的提高,导通电流显著增大。结果表明:薄型双漂移区器件较常规器件击穿电压提高16%,导通电阻下降24%。
在低掺杂漏SOI器件的N型漂移区中部注入P埋层形成BLD SOI器件。在埋氧层纵向电场和埋层附加电场的调制下,沟道边缘表面电场降低,优化漂移区浓度增大,导通电阻显著下降。在漏极引入低掺杂漏区,缓解了漏结的曲率效应,击穿电压增大。结果表明:埋层低掺杂漏SOI结构较常规SOI器件击穿电压提高29%,导通电阻下降22%。在理论的指导下,实验研制了超过700V的SOI高压器件。
提出双面阶梯埋氧层部分SOI高压器件结构,称为DSB PSOI。双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布;耗尽层通过源极下硅窗口向硅衬底扩展,埋氧层中纵向电场加强,提高了击穿电压,且缓解了自热效应。获得器件结构参数间二维的优化关系。结果表明:在保持导通电阻较低的情况下,双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58%,温度降低10-30K。
As a key device in high voltage integrated circuit,lateral high-voltage device has been deeply investigated by many scholars.With the quick development of semiconductor technology,the power devices and conventional low-voltage devices are scaled down.Because of the 2-D nature of electrical field in the drift region the 1-D model could not explain deeply the physical mechanism of the device.Owing the complexity of the boundary conditions,the 2-D model of the high-voltage device with some terminal technology is difficult to be solved. The model of the electrical field and breakdown voltage that can describe the interaction between the lateral and vertical electrical fields must be developed.It is a hotspot for many device designers to improve the trade-off between the breakdown voltage and the specific on-resistance of the high-voltage device.Novel thin drift region high-voltage device compatible with CWOS technology is an important developing trend of power semiconductor technology.
In this dissertation,the 2-D breakdown voltage models and the new structures to improve the trade-off between the breakdown voltage and the on-resistance of the thin drift region high-voltage device are investigated.A 2-D surface electrical field model of the thin drift region D-RESURF device and a breakdown voltage model of the thin drift region device with step doping profile are firstly proposed.Three new structure of high-voltage devices are developed, i.e.the thin double drift region high voltage device,the low doped drain SOI high voltage device with P buffed layer and the PSOI high voltage device with double-faced step buffed oxide layer,and the partial experiments are carried out.
The 2-D model for the surface electrical field of the D-RESURF device with sturface implanted P_b region is developed based on Poisson equation.The vertical electrical field influences strongly the surface electrical field when the drift region is thin.Besed on the model, the influence of the structure parameters on the coupling effect between the vertical electrical field and the surface electrical field has been examined.The optimal criterion for the maximum breakdown voltage and the minimum on-resistance has also been obtained.The dependence of the breakdown voltage on drift region length and thickness is calculated.The 900V D-RESURF devices have been fabricated with the guide of the analytical model.The 2-D breakdown voltage model of the S-RESURF device for the incompletely depleted drift region is given.The characteristic of the S-RESURF device is investigated when breakdown occurs at the P_(body)N_e junction,N~+N_e junction and vertical PN junction.A 2-D RESURF criterion including the charge sharing effect is derived when optimum surface dectrical field is realized.
A 2-D breakdown voltage model of the thin drift region device with step doping profile is demonstrated.A new electrical field peak appears between two regions with different doping concentration by the interaction of the lateral electrical field.The surface electrical field peaks are reduced by the coupling of the vertical electrical field,which leads to more or less uniform field profile in drift region.Based on the model,the influence of the structure parameters on the charge sharing is investigated;the optimum relationship among the structure parameters of the high-voltage device is obtained.The current of the thin drift region device with surface step doping profile flows mostly on the surface of the drift region which reduces the on-resistance of the device.The thin dirft region device with step doping profile enhances the trade-off between the breakdown voltage and the on-resistance and has a better technology tolerance.
A structure of the thin double drift region is proposed.The current can flow mostly along the surface of the drift region because the doping concentration of the surface implanted N~- layer is very high and the on-resistance of the high-voltage device is declined.P buried layer is implanted under the channel region which improves the drift region electrical field distribution. The electrical field modulation of the P buried layer inducts a new electrical field peak in the surface electrical field which leads to more or less uniform field profile.For the same drift region doping dose,with the increase of the surface N~- layer's doping concentration and the decrease of the thickness,the drain current is enhanced greatly.The results show that the breakdown voltage of the thin double drift region device is increased by 16%and the on-resistance is decreased by 24%compared to the conventional device.
P buried layer is incorporated inside the N drift region of the SOI device with low doped drain,which is called BLD SOI device.By the influences of the buffed layer's additional electrical field and the buried oxide layer's vertical electrical field,the surface electrical field near the channel is reduced and the optimal drift region doping concentration is increased,so the on-resistance is decreased significantly.A low doped drain region is introduced near the drain which can reduce the drain curvature and enhance the breakdown voltage.The results show that compared to the conventional SOI device the breakdown voltage of the BLD SOI device is increased by 29%and the on-resistance is decreased by 22%.Over 700V SOI high voltage device is manufactured successfully with the guide of the model.
A novel structure of PSOI high voltage device with double-faced step buried oxide layer is proposed,which is called DSB PSOI.The surface electric field reaches nearly ideal uniform distribution due to the additive electric field modulation by double step buried oxide layer.A silicon window underneath the source helps to reduce self-heating. Depletion region spreads into the substrate and the vertical electric field in the buried layer is enhanced,which results in a higher breakdown voltage.A 2-D optimal relation between the structure parameters is also obtained.The results indicate that the breakdown voltage of DSB PSOI device is increased by 58%and temperature is declined by 10-30K in comparison to conventional SOI device,maintaining the low on-resistance.
引文
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