摘要
系统级和门级集成电路中的复用技术已经成为片上系统(SoC)设计的重要趋势,而如何实现数字集成电路中功能规则性的自动化提取是规则性设计和集成电路分析的核心问题。本文针对功能规则性的自动化提取问题开展了研究,论文工作包括:
1.为满足SoC设计中对IP多样性和灵活性的需求,提出一种针对接口电路的可定制可复用架构,并基于该架构实现了CF卡及MMC卡接口控制器的设计。根据接口控制电路结构通用特点,提出了由接口控制部分、数据通路部分及传输控制部分三部分组成的接口电路通用架构。通过可配置性和参数化的设计,使用户能够根据自己需要随意选择IP核支持的功能模式、总线位宽、FIFO深度及宽度等配置。FPGA验证结果表明,所设计的接口控制器能够实现预定功能。
2.提出一种二同构模型对电路结构进行描述,并基于该模型实现了一种集成电路规律性快速提取方法。通过对两两相连的标准单元进行特征提取比较并产生二同构子电路,对出现频数较高的二同构子电路进行扩展产生电路结构模板,进而提取所有与该模板相似的电路结构。在算法运行过程中,通过不断的删除已经匹配的顶点,可加快程序运行的速度。实验表明,利用基于二同构扩展模型的集成电路规律性提取算法能够使对电路中规律性结构进行提取时有的放矢,最大限度地保证了重复出现次数最多的结构得到优先提取。
3.针对数字集成电路规律性提取算法复杂度过高的问题,提出一种逐级对根节点进行分类的小规模频繁子电路的预提取算法—SFSE算法。通过对频繁边的直接扩展,实现了小规模频繁子电路的快速提取;利用门级电路中小规模频繁子电路与大规模频繁子电路间的结构依赖性,解决了候选子电路生成时根节点组合爆炸的问题。实验结果表明,该算法能够降低根节点的数量,使支持度高的候选子电路得到优先提取,并显著地减少了规律性提取的时间。该工作将数据挖掘方法应用到门级集成电路的规律性提取中,为门级集成电路规律性的自动化提取开辟了新的研究思路。
4.将数据挖掘方法用于数字集成电路规律性提取,提出了链状和扇形两种结构模板的规律性提取算法。采用压缩式存储及删除缓冲器结构等方法,降低了电路的存储空间。建立顺序相关边权值模型,将复杂的子电路的同构搜索转化为边权值序列的匹配问题。模板扩展过程利用剪枝策略删除非频繁子电路,提高了规律性提取效率。将模板的产生与子电路的同构搜索过程合并,简化了规律性提取流程。有效解决了大规模集成电路中规则性提取复杂度过高的问题。实验证明,与传统的规律性提取算法相比,基于扇形和链状模板的规律性提取算法,不仅能够降低规律性提取的时间,而且能够得到更好的规律性提取结果,同时还能作为一种规律性预提取算法对传统的规律性提取算法进行优化。
5.提出一种基于频繁模式挖掘的门级数字集成电路自动化分析流程,解决了传统数字集成电路手工分析整理效率低下的问题。提出了基于EDIF文件的电路结构自动显示方法,规范了标准单元排布方法,提出了一系列基本结构及特殊功能结构的提取和识别方法,同时建立了计数器和有限状态机的结构模型。最后通过对
一款32位定制指令集处理器及Strong ARM的Data-Path电路的层次化分析整理,表明所提出方法的有效性。期间所开发出的一系列自动化整理和提取的工具,被应用到实际工程项目中,极大的提高了电路分析整理的效率。
The reuse methodology at system and gate level has become an important trend for the system-on-chip (SoC), and extraction of functional regularity automatically in digital ICs (Integrated Circuits) is playing a kernel role in regular design and IC analysis. This thesis focuses on the algorithm of the functional regularity automated extraction problem, and presents five main contributions as follows:
1. In order to meet the needs of diversity and flexibility of IP (Intellectual Property) in SoC design, a customizable and reusable architecture for interface circuits is proposed, and based on this architecture, the CF (Compact Flash) card and MMC (Multi Media Card) host controller are realized. According to the common characteristics of interface control circuits, the interface controller circuits can be divided into three parts:the interface control section, the data path part and the transmission control part. Based on configurable and parametric design method, the IP core user can choose the function mode、FIFO (First In First Out) depth and width bus width and any other configuration freely. FPGA validation results show that the function of the interface host controllers can achieve the design goals.
2. A new model named two-isomorphic is proposed to describe the circuit, and based on this model, a novel algorithm which can be used to extract the regularity in digital integrated circuits is achieved. By extracting and analyzing the properties of all two connected standard cells in the circuits, a series of templates including two standard cells will be obtained. The template with a high frequency will be extended so that it becomes longer than two, and then the instances of all longer templates will be explored using the proposed algorithm. To reduce the complexity and accelerate the algorithm, the matched vertexes will be deleted gradually from the search space. Experiments show that this method can reduce the complexity of the regular extraction, and extract the most frequent structural first.
3. According to the problem of high complexity in extraction of functional regularity in digital ICs, a regularity pre-extraction algorithm named SFSE for small scale frequent subcircuits is proposed, which is capable of categorizing the root nodes gradually. By extending the frequent edges directly, the small frequent subcircuits can be extracted fast; and utilizing structure dependencies between small frequent subcircuits and big ones at gate level, the combination explosion problem of root nodes has been solved in the process of generating candidate subcircuits. Experimental results show that the proposed algorithm can reduce the number of root nodes effectively, extract the high frequency candidate subcircuits with high priority and reduce runtime of regularity extraction observably. It is anticipated that the data mining method may play an important complementary role to the extraction of regularity in digital ICs.
4. By using the method of data mining in the extraction of functional regularity in digital ICs, two novel templates called CHAIN and FAN generation algorithms are proposed. To save the memory, a more efficient compressed storage strategy and deleting the buffer structure method are used when dealing with very large scale ICs. By establishing sequence-dependent edge-weight model, the complex subcircuit isomorphism problem can be solved by comparing the edge weight sequences of the subcircuits. To reduce the complexity and accelerate the algorithm, the pruning strategy is introduced into the expending of the templates to delete non-frequent subcircuits gradually. By merging the template generation process and the subcircuit isomorphism searching process, the regularity extraction flow is simplified. Meanwhile, the problem of high complexity during the extraction of functional regularity in very large scale ICs has been solved effectively. Experimental results show that both the CHAIN and FAN algorithms are more effective and can obtain better circuit covering results faster than the SPOG and TREE methods, furthermore, both of the two algorithms can be used as the pre-extraction algorithm to improve the performance of the traditional algorithms.
5. Based on the extraction methods of frequent mode above, a gate level integrated circuit automatic analysis process is proposed, which can be used to enhance the work efficiency of traditional analysis. A circuit structure automatically display method based on EDIF file is proposed. With the help of two standard array methods of the cells, a series of extraction and identification methods for basic and special function structure are proposed, meanwhile, the structure models of counter and FSM are described. By successfully applying these methods to a32-bit ASIP and data-path circuits in Strong ARM, the validity of these methods are proved. These methods have been implemented successfully in industry projects, and replaced the traditional manual analysis at gate level. Furthermore, the complexity of the reverse analysis for VLSI is reduced, and the work efficiency can also be enhanced distinctly.
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