摘要
系统级和门级集成电路中的复用技术已经成为片上系统(SoC)设计的重要趋势,而如何实现数字集成电路中功能规则性的自动化提取是规则性设计和集成电路分析的核心问题。本文针对功能规则性的自动化提取问题开展了研究,论文工作包括：
1.为满足SoC设计中对IP多样性和灵活性的需求,提出一种针对接口电路的可定制可复用架构,并基于该架构实现了CF卡及MMC卡接口控制器的设计。根据接口控制电路结构通用特点,提出了由接口控制部分、数据通路部分及传输控制部分三部分组成的接口电路通用架构。通过可配置性和参数化的设计,使用户能够根据自己需要随意选择IP核支持的功能模式、总线位宽、FIFO深度及宽度等配置。FPGA验证结果表明,所设计的接口控制器能够实现预定功能。
2.提出一种二同构模型对电路结构进行描述,并基于该模型实现了一种集成电路规律性快速提取方法。通过对两两相连的标准单元进行特征提取比较并产生二同构子电路,对出现频数较高的二同构子电路进行扩展产生电路结构模板,进而提取所有与该模板相似的电路结构。在算法运行过程中,通过不断的删除已经匹配的顶点,可加快程序运行的速度。实验表明,利用基于二同构扩展模型的集成电路规律性提取算法能够使对电路中规律性结构进行提取时有的放矢,最大限度地保证了重复出现次数最多的结构得到优先提取。
3.针对数字集成电路规律性提取算法复杂度过高的问题,提出一种逐级对根节点进行分类的小规模频繁子电路的预提取算法—SFSE算法。通过对频繁边的直接扩展,实现了小规模频繁子电路的快速提取；利用门级电路中小规模频繁子电路与大规模频繁子电路间的结构依赖性,解决了候选子电路生成时根节点组合爆炸的问题。实验结果表明,该算法能够降低根节点的数量,使支持度高的候选子电路得到优先提取,并显著地减少了规律性提取的时间。该工作将数据挖掘方法应用到门级集成电路的规律性提取中,为门级集成电路规律性的自动化提取开辟了新的研究思路。
4.将数据挖掘方法用于数字集成电路规律性提取,提出了链状和扇形两种结构模板的规律性提取算法。采用压缩式存储及删除缓冲器结构等方法,降低了电路的存储空间。建立顺序相关边权值模型,将复杂的子电路的同构搜索转化为边权值序列的匹配问题。模板扩展过程利用剪枝策略删除非频繁子电路,提高了规律性提取效率。将模板的产生与子电路的同构搜索过程合并,简化了规律性提取流程。有效解决了大规模集成电路中规则性提取复杂度过高的问题。实验证明,与传统的规律性提取算法相比,基于扇形和链状模板的规律性提取算法,不仅能够降低规律性提取的时间,而且能够得到更好的规律性提取结果,同时还能作为一种规律性预提取算法对传统的规律性提取算法进行优化。
5.提出一种基于频繁模式挖掘的门级数字集成电路自动化分析流程,解决了传统数字集成电路手工分析整理效率低下的问题。提出了基于EDIF文件的电路结构自动显示方法,规范了标准单元排布方法,提出了一系列基本结构及特殊功能结构的提取和识别方法,同时建立了计数器和有限状态机的结构模型。最后通过对
一款32位定制指令集处理器及Strong ARM的Data-Path电路的层次化分析整理,表明所提出方法的有效性。期间所开发出的一系列自动化整理和提取的工具,被应用到实际工程项目中,极大的提高了电路分析整理的效率。
The reuse methodology at system and gate level has become an important trend for the system-on-chip (SoC), and extraction of functional regularity automatically in digital ICs (Integrated Circuits) is playing a kernel role in regular design and IC analysis. This thesis focuses on the algorithm of the functional regularity automated extraction problem, and presents five main contributions as follows:
1. In order to meet the needs of diversity and flexibility of IP (Intellectual Property) in SoC design, a customizable and reusable architecture for interface circuits is proposed, and based on this architecture, the CF (Compact Flash) card and MMC (Multi Media Card) host controller are realized. According to the common characteristics of interface control circuits, the interface controller circuits can be divided into three parts:the interface control section, the data path part and the transmission control part. Based on configurable and parametric design method, the IP core user can choose the function mode、FIFO (First In First Out) depth and width bus width and any other configuration freely. FPGA validation results show that the function of the interface host controllers can achieve the design goals.
2. A new model named two-isomorphic is proposed to describe the circuit, and based on this model, a novel algorithm which can be used to extract the regularity in digital integrated circuits is achieved. By extracting and analyzing the properties of all two connected standard cells in the circuits, a series of templates including two standard cells will be obtained. The template with a high frequency will be extended so that it becomes longer than two, and then the instances of all longer templates will be explored using the proposed algorithm. To reduce the complexity and accelerate the algorithm, the matched vertexes will be deleted gradually from the search space. Experiments show that this method can reduce the complexity of the regular extraction, and extract the most frequent structural first.
3. According to the problem of high complexity in extraction of functional regularity in digital ICs, a regularity pre-extraction algorithm named SFSE for small scale frequent subcircuits is proposed, which is capable of categorizing the root nodes gradually. By extending the frequent edges directly, the small frequent subcircuits can be extracted fast; and utilizing structure dependencies between small frequent subcircuits and big ones at gate level, the combination explosion problem of root nodes has been solved in the process of generating candidate subcircuits. Experimental results show that the proposed algorithm can reduce the number of root nodes effectively, extract the high frequency candidate subcircuits with high priority and reduce runtime of regularity extraction observably. It is anticipated that the data mining method may play an important complementary role to the extraction of regularity in digital ICs.
4. By using the method of data mining in the extraction of functional regularity in digital ICs, two novel templates called CHAIN and FAN generation algorithms are proposed. To save the memory, a more efficient compressed storage strategy and deleting the buffer structure method are used when dealing with very large scale ICs. By establishing sequence-dependent edge-weight model, the complex subcircuit isomorphism problem can be solved by comparing the edge weight sequences of the subcircuits. To reduce the complexity and accelerate the algorithm, the pruning strategy is introduced into the expending of the templates to delete non-frequent subcircuits gradually. By merging the template generation process and the subcircuit isomorphism searching process, the regularity extraction flow is simplified. Meanwhile, the problem of high complexity during the extraction of functional regularity in very large scale ICs has been solved effectively. Experimental results show that both the CHAIN and FAN algorithms are more effective and can obtain better circuit covering results faster than the SPOG and TREE methods, furthermore, both of the two algorithms can be used as the pre-extraction algorithm to improve the performance of the traditional algorithms.
5. Based on the extraction methods of frequent mode above, a gate level integrated circuit automatic analysis process is proposed, which can be used to enhance the work efficiency of traditional analysis. A circuit structure automatically display method based on EDIF file is proposed. With the help of two standard array methods of the cells, a series of extraction and identification methods for basic and special function structure are proposed, meanwhile, the structure models of counter and FSM are described. By successfully applying these methods to a32-bit ASIP and data-path circuits in Strong ARM, the validity of these methods are proved. These methods have been implemented successfully in industry projects, and replaced the traditional manual analysis at gate level. Furthermore, the complexity of the reverse analysis for VLSI is reduced, and the work efficiency can also be enhanced distinctly.
引文
[1.1]吕勇强.超大规模集成电路性能驱动的布局算法研究.清华大学博士学位论文.2006.
[1.2]G. E. Moore. Cramming more components onto integrated circuits. IEEE Electron Magazine, April 1965,38(8):114-117.
[1.3]Semiconductor Industry Association (SIA). International Technology Roadmap for Semiconducotrs.2007 Edition. [Online]:http://public.itrs.net.
[1.4]魏少军.SoC设计方法学(一).电子产品世界,2001年09期.
[1.5]魏少军.SoC设计方法学(二).电子产品世界,2001年11期.
[1.6]H. Chang, Surviving the SOC revolution, Kluwer Academic Publishers, November 1999.
[1.7]Hunt, M. Rowson, J.A. Blocking in system on a chip. IEEE Spectrum. On page(s):35-41.Nov.1996(IP).
[1.8]Lesley Shannon.半导体产业IP复用现状概述.多伦多大学.
[1.9]张自然.IP核复用：SoC腾飞之“翼”(3).中国电子报,2007年6月.
[1.10]Poulin, Jeffrey, Measuing software reuse, Addison-Wesley, January 1997.
[1.11]赵康.基于专用指令处理器的片上系统综合技术研究.清华大学博士学位论文.2009.
[1.12]R. Chris, Leibson Steve. Engineering the complex SOC:fast, flexible design with configurable processors. Prentice Hall, June 2004.
[1.13]Tensilica Inc. [Online]:www.tensilica.com.
[1.14]蒋安平,超深亚微米工艺时代集成电路设计领域所面临的技术挑战,中国集成电路,Vol.86,2006,29-33.
[1.15]龙迪.信号流驱动的模拟集成电路自动布局方法.清华大学博士学位论文.2007.
[1.16]A. Nardi, A. L. Sangiovanni-Vincentelli. Logic synthesis for manufacturability [J]. IEEE Design& Test of Computers,2004,5(3):192-199.
[1.17]V. Kheterpal, V. Rovner, T. G Hersan, et al. Design methodology for IC manufacturability based on regular logic bricks. Proceedings of Design Automation Conference, Anaheim,2005:353-358.
[1.18]A. P. E. Rosiello, F. Ferrandi, D. Pandini, et al. A hash-based approach for functional regularity extraction during logic synthesis. Proceedings of IEEE Computer Society Annual Symposium on VLSI, Porto Alegre,2007:92-97.
[1.19]S. Das, S. P. Khatri. An efficient and regular routing methodology for datapath designs Using Net Regularity Extraction. IEEE Transactions on Computer-Aided Design,2001,21(1):93-101.
[1.20]ANSI/EIA-618. Electronic design interchange format version 300[S].
[1.21]ANSI/EIA-618. Electronic design interchange format version 400[S].
[2.1]K. Michael and B. Pierre, Reuse methodology manual for system-on-chips designs, Kluwer Academic Publishers,1999, Second Printing.
[2.2]I. Parulkar, M. A. Breuer, C. A. Njinda. Extraction of a high-level structural representation form circuit description with applications to DFT/BIST. Proceedings of IEEE/ACM Design Automation Conference,1994:345-350.
[2.3]N. Zhang, C. W. Donald. Speeding up VLSI layout verification using fuzzy attributed graphs approach. IEEE Transactions on Fuzzy Systems,2006, 14(6):728-737.
[2.4]C. Ebeling, O. Zajicek. Validating VLSI circuit layout by wirelist comparison. Proceedings of the Conference on Computer Aided Design, Santa Clara, 1983:172-173.
[2.5]M. Ohlrich, C. Ebeling, E. Ginting, and L. Sather, SubGemini:identifying subcircuits using fast subgraph isomorphism algorithm, Proceedings of the 30th ACM/IEEE Conference,1993, pp:31-37.
[2.6]徐玉婷.基于子图同构的晶体管级电路门级模型抽取的研究.电子科技大学硕士学位论文.2004.
[2.7]K.-T. Huang, D. Overhauser. A novel graph algorithm for circuit recongnition. Proc. IEEE International Symposium on Circuits and Systems.1995:1695-1698.
[2.8]N. Vijaykrishnan, N. Ranganathan. SUBGEN:a genetic approach for subcircuit extraction, Proceedings of the 9th International Conference on VLSI Design, Bangalore, India, Jan.1996, pp.343-345.
[2.9]W. H. Chang, S.D. Tzeng, C. Y. Lee. A novel subcircuit extraction algorithm by recursive identification scheme. Proceedings of IEEE International Symposium on Circuits and Systems, Sydney, Australia,2001, Vol.5, pp.491-494.
[2.10]N. Zhang and D. C. Wunsch, A novel subcircuit extraction algorithm using heuristic dynamic programming (HDP). Proceedings of 2002 International Conference on VLSI, Las Vegas, NV, Jun.24-27,2002, pp.38-44.
[2.11]Nikolay, Rubanov. SubIslands:the probabilistic match assignment algorithm for subcircuit recognition. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.22:26-38.
[2.12]A. Lester, P. Bazargan-Sabet, A. Greiner. YAGLE:a second generation functional abstractor for CMOS VLSI circuits. Proceedings of the 10th International Conference on Microelecltronics,1998:265-268.
[2.13]ConformalTM LEC Logic equivalence checker and transformalTM LTX logic transistor extraction user manual. Version 3.0. August 2001.
[2.14]Cadence[OL]www.cadence.com/products/functional_ver/conformal/index.aspx.
[2.15]A. Chowdhary, S. Kale, et al. Extraction of functional regularity in datapath circuits. IEEE Transactions on Computer-Aided Design,1999,18(9):1279-1296.
[2.16]杨长旗.超大规模集成电路混合模式布局算法与系统设计.清华大学博士学位论文.2004.
[2.17]T. T. Ye and G. D. Micheli. Data path placement with regularity. Proceedings of ICCAD 2000.
[2.18]C.M. Kyung, HK386, an x86-compatible 32 bit CISC microprocessor, Proceedings of IEEE ASP-DAC,1997 pp661-662.
[2.19]J.S. Yim and C.M.K Kyung, Datapath layout optimization using genetic algorithm and simulated annealing, IEEE Proc.-Compute Digit Tech. Vol.145 NO 2, March 1998.
[2.20]D. S. Rao, F. J. Kurdahi. Partitioning by regularity extraction. Proceedings of IEEE/ACM Design Automation Conference, Jun.1992, pp.235-238.
[2.21]D. S. Rao, F. J. Kurdahi. On clustering for maximal regularity extraction. IEEE Trans, on Computer-Aided Design,1993,12(8):1198-1208.
[2.22]M. R. Corazao, M. A. Khalaf, L. M. Guerra, M. Potkonjak, and J. M. Rabaey, Performance optimization using template mapping for datapathe-intensive high-level synthesis, IEEE Trans, on Computer-Aided Design, Vol.15,pp.877-887, Aug.1996.
[2.23]S. R. Arikati, R. Varadarajan. A signature based approach to regularity extraction. Proceedings of International Conference on Computer-Aided Design, Washington:IEEE,1997:542-545.
[2.24]T. Kutzschebauch. Efficient logic optimization using regularity extraction. Proceedings of International Conference on Computer-Aided Design, Austin: IEEE,2000:487-493.
[2.25]A. Chowdhary, S. Kale, P. Saripella, et al. A general approach for regularity extraction in datapath circuits. Proceedings of IEEE International Conference on Computer-Aided Design,1998:332-338.
[2.26]A. Chakraborty, D. Pandini, et al. Evaluating regularity extraction in logic synthesis. Proceedings of iEEEISSCAS,2005:641-644.
[2.27]A. Chowdhary and R. K. Gupta. A Methodology for Synthesis of Data Path Circuits. IEEE Design& Test of Computers,2002, pp.90-100.
[2.28]G. Odawara, et al. Partitioning and placement technique for CMOS gate arrays. IEEE Trans, on Computer-Aided Design, pages 355-363, May 1987.
[2.29]R. X. T. Nijssen and J. A. G. Jess. Two-dimensional datapath regularity extraction. Proceedings of the 5th ACM/IEEE Physical Design Workshop, Restion, Virginia,1996.
[2.30]R. X. T. Nijssen and C. A. J. van Eijk. Regular layout generation of logically optimized datapaths. Proceedings of the International Symposium on Physical Destin, Pages42-47,1997.
[2-31]郎荣玲,戴冠中.集成电路的模块生成与选择算法.电了学报,2005,33(11)：1955-1958.
[2.32]李长青,汪雪林,彭思龙.辐射路匹配：从门级到功能模块级的子电路提取算法.计算机辅助设计与图形学学报,2006,18(9)：1377-1382.
[2.33]蒿杰,彭思龙.基于超图模型的大规模门级网表层次化聚类算法.计算机辅助设计与图形学学报,2009,21(1)：44-52.
[2.34]H. Nakao, O. Kitada, M. Hayashikoshi, K. Okazaki, and Y. Tsujihashi. A high density datapath layout generation method under path delay constraints, IEEE 1993 Custom Integrated Circuits Conference.
[2.35]J.S.Yim and C.M.Kyung, Datapath layout optimisation using genetic algorithm and simulated annealing, IEEE Proc.-Comput. Digit. Tech. Vol.145 No2, March 1998.
[2.36]P. Lenne and A. Grieding. Practical experiences with standard-cell based datapath design tools, Proceedings of 35th DAC,1998.
[2.37]R.X.T. Nijssen and C.A.J. van Eijk. GreyHound:A methodology for utilizing datapath regularity in standard design flows, Integration, the VLSI Journal 25, 1998, pplll-135.
[2.38]Y. W. Lin, M. M. Sadowska and W. P. Maly. Layout generator for transistor-level high-density regular circuits, IEEE Transactions on Computer-Aided Design, 2010,29(2):197-210.
[2.39]Y. Ran and M. Marek-Sadowska. Designing a via-configurable regular fabric, Proceedings of CICC,2004. pp.423-426.
[2.40]C. Q. Yang, X. L. Hong, Y. C. Cai, W. T. Hou, et al. Standard-cell based data-path placement utilizing regularity. Proceeding of 5th International Conference on ASIC,2003 Beijing:97-100.
[2.41]吕雅帅.ASIP指令集自动扩展系统的研究与实现.国防科学技术大学计算机学院硕士学位论文,2006.
[2.42]L. Pozzi, M. Vuletic, and P. Ienne. Automatic topology-based identification of instruction-set extensions for embedded processor. Technical Report 01/377, NSwiss Federal Institute of Technology Lausanne (EPFL),2001.
[2.43]J. Cong, Y. Fan, G. Han, and Z. Zhang. Application-specific instruction generation for configurable processor architectures. Proceedings of ACM/SIGDA 12th international symposium on Field Programmable Gate Arrays, Monterey, California,2004:183-189.
[2.44]M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton and V. A. Sangiovanni. HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. Proceedings of the international symposium on Hardware/software codesign, Estes Park, Colorado,2002: 151-156.
[2.45]Y. Lu, L. Shen, L. Huang, Z. Wang and N. Xiao. Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. Proceedings of the Design Automation Conference (DAC), Anaheim, California,2008:197-200.
[2.46]D. W. Dobberpuhl. Circuits and technology for digital's StrongARM and ALPHA microprocessors. Proceedings of IEEE Conference on Advanced Research in VLSI, Ann Arbor,1997:2-11.
[2.47]J. L. White, M.-J. Chung, et al. Efficient algorithms for subcircuit enumeration and classification for the module identification problem. IEEE International Conference on:Computer Design:VLSI in Computer and Processors. Austin: IEEE,2001:519-522.
[2.48]G. H. Chisholm, S. T. Eckmann, et al. Understanding integrated circuits. IEEE Design& Test of Computers,1999(2):26-37.
[2.49]M. C. Hansen, H. Yalcin, J. P. Hayes. Unveiling the ISCAS-85 benchmarks:a case study in reverse engineering. IEEE Design& Test of Computers,1999, 16(3):72-80.
[2.50]T. Sobh, M. K. Elleithy and S. Patel. Reverse engineering of VLSI chips:a roadmap. Journal of Engineering and Applied Sciences,2007,2(2):290-298.
[3.1]史江义.基于IP核的SoC设计关键技术研究.西安电子科技大学博士学位论文.2007.
[3.2]http://www.arc.com.
[3.3]P. J. Bricaud. IP reuse creation for system-on-a-chipdesign. Proceedings of the IEEE Custom Integrated Circuits,1999,395-401. May 1999.
[3.4]潘伟涛,谢元斌,史江一.基于SoC可配置CF/CF+卡控制器的设计,电子器件,2008,31(4)：1288-1292.
[3.5]潘伟涛,郭晋亮,谢元斌,史江一.基于SoC低功耗MMC卡控制器的设计,电子器件,2008,31(5)：1704-1708.
[3.6]G. Koulouras, et al. Embedded compact flash. IEEE Circuits and Devices Magazine,2005,21 (4):27-34.
[3.7]秦亚杰等.一种用于数码相机芯片的CF卡控制电路设计.复旦学报,2003.42(1)：114-118.
[3.8]张宏伟等.基于CF卡的数字电视接收端存储系统的硬件设计.电了工程师.2006.32(4)：36-39.
[3.9]Compact Flash Association, CF+and Compact Flash specification revision 3.0,2004/12/23.
[3.10]王智等.基于乒乓操作的异步FIFO设计及VHDL实现.电子工程师,2005.31(6)：13-16.
[3.11]钏雄光,戎蒙恬等.基于FPGA的PCMCIA加密网卡.计算机工程.2005.31(13)：179-180.
[3.12]Clifford E Cummings. Simulation and synthesis techniques for asynchronous FIFO design. Sunburst Design, Inc:6～7,2002.
[3.13]刘新宁,王超.一种快速CRC算法的硬件实现,电子器件.2003.26(1)：88-91.
[3.14]D. Helal, et al. UWB file transfer between mobile terminals using Multi-Media Card standard interface and Blue Tooth as a control radio. Ultra-Wideband IEEE International Conference on 2005,609-614.
[3.15]MMCA Technical Committee, The Multi-Media Card system specification Version 4.1,2005/04
[3.16]M. Keating, P. Bricaud. Reuse methodology manual for system-on-a-chip designs. Third Edition. New York. Kluwer Academic Publishers,2002.
[3.17]L. Benini, A. Bogliolo, G. DeMicheli. A Survey of design techniques for system-level dynamic power management. IEEE transactions on Very Large Scale Integration (VLSI) systems,2000.8(3):299-316
[3.18]M. Donno, A. Ivaldi, L. Benini, E. Macii. Clock-tree power optimization based on RTL clock-gating. Proceedings of the Design Automation Conference. Anaheim, CA, USA,2003:622-627
[3.19]Synopsys power compiler manual, Release U-2005.06-QA, June 2005.
[3.20]史江一,朱志炜,方建平,等.基于IP核的8位微控制器设计.电子器件.2007.30(1)：148-151.
[3.21]刘伟锋,庄奕琪,刘锋,等.高性能嵌入式UART IP核的设计.电子器件.2007.30(4)：1275-1278.
[3.22]何威,庄奕琪,汤华莲.一种快速IrDA的设计与FPGA实现.现代电子技术.2006.17：9-11.
[3.23]黄鑫,庄奕琪,靳刚.可重用SPI接口IP核的设计及实现.西安电子科技大学2006年研究生学术年会会议论文.361-365.
[4.1]G. Karypis, R. Aggarwal, V. Kumar, et al. Multilevel hypergraph partitioning: applications in VLSI domain. IEEE Transactions on Computer-Aided Design of Integrated Circuit s and Systems,1999,7 (1):1088-1096.
[4.2]G. Karypis, V. Kumar. Analysis of multilevel graph partitioning. Minneapolis: University of Minnesota,1998.
[4.3]Y. Cheon, D. F. Wong. Design hierarchy guided multilevel circuit partitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(4):420-427.
[4.4]G. J. Nam, S. Reda, C. J. Alpert, et al. A fast hierarchical quadratic placement algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2006,25(4):678-691.
[4.5]W. Kim, H. Shin. Hierarchical LVS based on hierarchy rebuilding. Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama,1998: 379-384.
[4.6]Cadence. LEF/DEF language reference product version 5.4.2003.1, http://openeda.org/download_lefdef.html
[4.7]刘毅.超大规模集成电路时钟网络设计与优化算法研究.清华大学博士论文.2003.
[4.8]T. Manikas. YAL language specification for netlists.1998.9, http://www. ee. utulsa.edu/～tmanikas/VLSI/y al-language.pdf
[4.9]D. E. Thomas, P. R. Moorby. The verilog hardware description language (fourth edition).刘明业,蒋敬旗,刁岚松等译.硬件描述语言Verilog(第四版).清华大学出版社,2001.8.
[4.10]乔长阁,边计年.薛宏熙等译VHDL简明教程.清华大学出版社,1997.
[4.11]潘伟涛,谢元斌,郝跃,史江一.二同构扩展数字集成电路规律性提取算法.西安电子科技大学学报,2009,36(3)：452-457.
[4.12]王晨.结构数据挖掘与处理的若干问题研究.复旦大学博士学位论文.2005.
[4.13]苏浩航,张义门,张玉明,满进财.基于压缩式双共轭梯度算法对大规模电源／地线网络的快速分析.计算机辅助设计与图形学学报.2007,19(10)：673-676.
[4.14]http://www.pld.ttu.ee/-maksim/benchmarks/iscas89/.
[4.15]赵康,边计年,董社勤.基于集束式整数线性规划模型的专用指令集自动定制.计算机辅助设计与图形学学报,19(10),2007.10：1229*1234.
[5.1]王映龙,杨炳儒,宋泽峰等.一种挖掘最大频繁子图的新算法.系统仿真学报,2008,20(18)：4872-4877.
[5.2]B. Berendt, A. Hotho, G Stumme. Towards semantic web mining. Ian Horrocks and James Hendler. International Semantic Web Conference (ISWC). Sardinia, Italy:Springer-Verlag,2002.264-278.
[5.3]M. Girvan, M. E. J. Newman. Community structure in social and biological networks. Proc Natl Acad Sci,2001,99(12):7821-7826.
[5.4]N. Kashtan, S. Itzkovitz, R. Milo, U. Alon. Efficient sampling algorithm for estimating subgraph concentrations and detecting network motifs. Bioinformatics, 2004,20(11):1746-1758.
[5.5]N. Przulj, D. G. Corneil, I. J. urisica. Efficient estimation of graphlet frequency distributions in protein-protein interaction networks. Bioinformatics,2006, 22(8):974-980.
[5.6]M. Koyuturk, Y. Kim, S. Subramaniam, et al. Detecting conserved interaction patterns in biological networks. Journal of Computational Biology,2006, 13(7):1299-1322.
[5.7]M. Deshpande, M. Kuramochi, G. Karypis. Frequent substructure based approaches for classifying chemical compounds. IEEE Transactions on Knowledge and Data Engineering,2005,17(8):1036-1050.
[5.8]S. Parthasarathy, M. Coatney. Efficient discovery of common substructures in macromolecules. Proc of 2002 IEEE International Conference on Data Mining (ICDM) [C]. Maebashi City, Japan:IEEE,2002.362-369.
[5.9]胡黔楠.化学信息学中的数据挖掘.中南大学博士学位论文.2004.
[5.10]X Yan, J Han. GSpan:Graph-based substructure pattern mining. Proceedings of 2002 IEEE International Conference Data Mining (ICDM). Maebashi City, Japan:IEEE,2002.721-724.
[5.11]A. Inokuchi, T. Washio, H. Motoda. Complete mining of frequent patterns from graphs:Mining graph data. Machine Learning,2003,50(3):321-354.
[5.12]M. Hong, H. Zhou, W. Wang, B. Shi. An efficient algorithm of frequent connected subgraph extraction. Proceedings of the 7th Pacific-Asia Conference on Knowledge Discovery and DataMining (PAKDD2003). Volume 2637 of Lecture Notes in Computer Science. Seoul, South Korea:Springer-Verlag,2003. 40-51.
[5.13]X. Yan, J. Han. CloseGraph:Mining closed frequent graph patterns. Proceedings of the 9th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining (KDD2003). Washington.DC, USA:ACM,2003.286-295.
[5.14]J. Huan, W. Wang, J. Prins. Efficient mining of frequent subgraph in the presence of isomorphism. Proceedings of 2003 IEEE International Conference on Data Mining (ICDM'03). Melbourne, Florida USA:IEEE,2003.549-552.
[5.15]M. Kuramochi, G. Karypis. An efficient algorithm for discovering frequent subgraphs. IEEE Transation Knowledge and Data Eng,2004,16(9):1038-1051.
[5.16]E. Gudes, S. E. Shimony, N. Vanetik. Discovering frequent graph patterns using disjoint paths. IEEE Transactions on Knowledge and Data Engineering,2006, 18(11):1441-1456.
[5.17]K. Yoshida, H. Motoda, N. Indurkhya. Graph-based induction as a unified learning framework. Journal of Applied Intelligence,1994,4:297-328.
[5.18]S. Ghazizadeh, S. Chawathe. SeuS:structure extraction using summaries. Proceedings of the 5th International Conference on Discovery Science. Lubeck, Germany:ACM,2002.71-85.
[5.19]N. Vanetik, E. Gudes, S. E. Shimony. Computing frequent graph patterns from semistructured data. Proceedings of 2002 IEEE International Conference on Data Mining (ICDM). Maebashi City, Japan:IEEE,2002.458-465.
[5.20]高琳,覃桂敏,周晓峰.图数据中频繁模式挖掘算法研究综述.电子学报,2008, 36(8)：1603-1609.
[5.21]W T Tutte. Graph theory. Cambridge University Press,2001.
[5.22]潘伟涛,郝跃,谢元斌,史江一.小规模频繁子电路的规律性预提取算法.计算机辅助设计与图形学学报,2010,22(2)：226-233.
[6.1]Y. Feng, H. A. Mantooth. Algorithms for aautomatic model topology formulation. IEEE Transation on Computer-Aided Design,2009,28(4):502-515.
[6.2]J. R. Ullmann. An algorithm for subgraph isomorphism. Journal of the Association for Computer Machinery,1976,23(1):31-42.
[6.3]B. Falkenhainer, K. D. Forbus, D. Gentner. The structure-mapping engine: algorithms and examples. Artificial Intelligence,1989,41(1):1-63.
[6.4]B. T. Messmer, H. Bunke. A decision tree approach to graph and subgraph isomorphism detection. Pattern Recognition,1999,32(12):1979-1998.
[6.5]B. T. Messmer, H. Bunke. Subgraph isomorphism in polynomial time [OL]. http://citeseer.nj.nec.com/messmer95subgraph.html.
[6.6]F. Hopcroft, J. Wong. Linear time algorithm for isomorphism of planar graphs. Proceedings of the 6'Annual ACM Symposium on Theory of Computing, Seattle, 1974:172-184.
[6.7]A. V. Aho, J. E. Hopcroft, J. D. Ullman. The design and analysis of computer algorithm. Boston, Massachusetts:Addison Wesley,1974.
[6.8]D. G. Corneil, C. C. Gotlieb. An efficient algorithm for graph isomorphism. Journal of the Association for Computer Machinery,1970,17(1):51-64.
[6.9]F. Brglez, D. Bryan, K. Kozminski. Combinational profiles of sequential benchmark circuits. ISCAS,1989:1929-1934.
[6.10]潘伟涛,谢元斌,郝跃,史江义.基于扇形模板的数字集成电路规律性提取算法.电子学报,2010,38(1)：199-203.
[7.1]衣晓飞.集成电路芯片图像处理技术的研究.国防科学技术大学博士学位论文.2001.
[7.2]T. E. Doom. Design recovery for combinational logic exploiting boolean relationships, doctoral dissertation, Michigan State Univ., Dept. of Computer Science and Engineering East Lansing, Mich.,1998.
[7.3]陈瑞森.基于逆向工程的MPU及其改进芯片的设计.厦门大学硕士学位论文.2006.
[7.4]J. L. White. Candidate subcircuit enumeration for module identification in digital circuits, doctoral dissertation, Michigan State Univ., Dept. of Computer Science and Engineering East Lansing, Mich.,2000.
[7.5]K. J. Singh, P. A. Subrahmanyam. Extracting RTL modules from transistor netlists. Proceedings of IEEE International Conference on Computer-Aided Design,1995:11-17.
[7.6]R. Torrance and D. James. Reverse engineering in the semiconductor industry. IEEE 1997 Custom Integrated Circuits Conference.
[7.7]尹金荔.基于相似性度量的图模式挖掘研究.西安电子科技大学硕士学位论文.2007.
[7.8]J. Cong. Timing closure based on physical hierarchy. Proceedings of ACM International Symposium Physical Design, San Diego,2002:170-174.
[7.9]M. Y. Niamat, D. Bitter, M. M. Jamali. FPGA implementation of hierarchical clustering algorithms. Proceedings of IEEE International Symposium on Circuits and Systems, Monterey,1998:70-73.
[7.10]常睿.网络数据处理器验证技术.西安电子科技大学硕士学位论文.2009.
[7.1I]王庆成.面向IP包处理的硬件多线程处理器研究与设计.西安电子科技大学硕士学位论文.2010.
[7.12]蔡珊.嵌入式32位RISC处理器中存储管理单元的研究与设计.西安电子科技大学硕士学位论文.2009.
[7.13]王琪.嵌入式处理器中高速缓存的研究与设计.西安电子科技大学硕士学位论文.2009.
[7.14]董博辉.多核处理器高性能ALU单元设计研究.西安电子科技大学硕士学位论文.2010.
[7.15]刘宇.基于多核SoC的高性能数据交换接口设计研究.西安电子科技大学硕士学位论文.2010.
[7.16]陈焱辉.嵌入式SDRAM控制器设计研究.西安电子科技大学硕士学位论文.2009.
[7.17]张国霞.嵌入式SRAM/SSRAM/FLASH控制器的设计与关键面积算法的研究.西安电子科技大学硕士学位论文.2009.
[7.18]李振涛,陈书明.全定制电路功能模型提取的若干新算法.计算机辅助设计与图形学学报,2007,19(5)：628-634.