摘要
随着计算机网络和通信系统的发展,对接口电路和外围器件在执行速度上提出了更高的要求。本设计中的网络处理器外接SRAM,主要用于存储网络处理器分组描述符,队列描述符以及索引表,SRAM控制接口完成控制网络处理器内部的异构并行多处理器对片外SRAM资源的存取访问,将不同处理器的专用指令转化成SRAM可以识别的操作命令,并完成相应的网络操作。
针对网络应用,本设计中的SRAM控制接口具有以下三个特点:第一, SRAM控制接口支持网络处理中不同指令集异构并行多处理器共享片外SRAM;第二,除了支持读和写操作以外,根据网络数据处理需要,SRAM控制接口还能够完成读锁操作、写解锁操作、解锁操作、POP操作、PUSH操作以及位写操作等6种操作,在功能上能够更有效地支持网络数据处理,提高总线利用率;第三,SRAM控制接口能够根据片外SRAM存储容量的变化进行容量配置,即:当多处理器对不同存储容量的片外SRAM进行访问时,不需要改变SRAM控制接口模块的硬件结构,只需要配置SRAM控制器单元的控制状态寄存器的相应参数,就可以实现对片外SRAM的正确操作。
基于上述网络应用SRAM访问需求的特点,本设计完成了对SRAM控制接口模块的RTL级语言描述,功能仿真和性能仿真结果表明SRAM控制接口可以完成多核处理器对片外SRAM的访问,在SMIC 0.13μm工艺下达到200MHz的执行性能,能够支持2.5Gbps网络线速传输要求,完成了预期的设计目标,满足了课题的需求。
With the development of computer network and communications system, the interface circuits and peripheral devices need to be operated at much higher speed. In this design, the network processor is connected to SRAM, which is used to store the packet descriptors, the queue descriptors and the index tables for the network processor. The SRAM control interface is used to control the multi-processor to access the resource of the external SRAM, translate specified commands from different processors into commands which SRAM can execute, and complete the relevant network operation.
In allusion to the network application, the SRAM control interface presented in this design has three characteristics. First of all, the SRAM control interface supports the heterogeneous parallel multi-processor of the network processor to share the resource of external SRAM. Moreover, other than supporting write and read operations, the SRAM control interface can do more operations, such as read_lock, write_unlock, unlock, pop, push and bit_wr operations. That means the SRAM control interface is more effective to support network data operations and to improve the utilization of the bus. Furthermore, according to the change of external SRAM storage capability, the SRAM control interface can make a capability configuration. That means, when the multi-processor accesses external SRAM, the SRAM control interface does not need to change its hardware structure, but just needs to change the parameter of CSR(it refers to Control State Register) in SRAM controller unit.
Based on before-mentioned characteristics, this design completes RTL level description of the SRAM control interface module. Function simulation and performance simulation results show that the SRAM control interface can complete the external SRAM access for multi-processor and achieve the implementation performance up to 200MHz based on the SMIC 0.13μm CMOS processes.
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