摘要
干扰是电子对抗中的一个重要分支。本设计利用直接数字合成技术(DDS)和延时叠加来产生干扰信号，本设计由两片FPGA实现，一片完成DDS和延时叠加的功能，另一片完成测试和控制的功能。本论文对干扰信号产生电路的原理、软件设计实现、硬件设计实现进行研究，并给出了该设计的部分测试结果。
本论文首先介绍了系统设计的思想，FPGA的基本结构和设计流程，电源设计，说明了各芯片的特点和作用，JTAG接口等；接着介绍了干扰信号产生电路的DDS设计的原理，实现和仿真测试结果及MATLAB的仿真结果；然后给出了干扰信号产生电路的延时叠加模块实现及其主要模块的仿真测试结果及MATLAB的仿真结果；然后对本设计的测试模块的实现及所使用的部分硬件进行了介绍，所有模块的实现都是采用Verilog HDL；最后介绍了板极调试所用到的几个工具：数字示波器，COMAPI串口收发程序软件和QuartusⅡ自带的工具SignalTapⅡ，以及给出了部分测试过程和结果。
Jamming is an important branch in the Electronic Countermeasure (ECM).This designutilizes the direct digital synthesis technology (DDS) and delay-superposition to generatejamming signals. This design is realized with two FPGA chips. One chip implements DDSand delay-superposition functions, and the other implements test and controlling functions.This thesis studies the principle of the circuit that generates jamming signals, therealization of software and the realization of hardware, and also provides some test results.
This thesis firstly introduces the thought of system design, the basic structure anddesign procedure of FPGA, the power supply design, and the characteristics and functionsof some chips and the JTAG interface. Then this thesis introduces the principle of DDS, therealization of DDS, and the simulation test results of MATLAB and QUARTUSⅡ. Thirdlythis thesis provides the realization of the delay-superposition module, and the simulationtest results of MATLAB and QUARTUSⅡ. The realization of the test module and some ofthe hardware that used in the test module are given. This design adopts Verilog HDLlanguage to realize all kinds of functions. Finally this thesis introduces several tools whichare used in debugging: Digital oscillograph, COMAPI which is a kind of software used forserial transceiver, and SignalTapⅡattached of QuartusⅡ, and provides some test processand results.
引文
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